On Mon, Jun 30, 2025 at 02:48:25PM +0100, Robin Murphy wrote: > On 29/06/2025 9:58 pm, Geraldo Nascimento wrote: > > Current code enables only Lane 0 because pwr_cnt will be incremented on > > first call to the function. Let's reorder the enablement code to enable > > all 4 lanes through GRF. > > As usual the TRM isn't very clear, but the way it describes the > GRF_SOC_CON_5_PCIE bits does suggest they're driving external input > signals of the phy block, so it seems reasonable that it could be OK to > update the register itself without worrying about releasing the phy from > reset first. In that case I'd agree this seems the cleanest fix, and if > it works empirically then I think I'm now sufficiently convinced too; > > Reviewed-by: Robin Murphy <robin.murphy@xxxxxxx> Hi everyone, Patches 1 and 2 of this series were merged thhrough pci git but patches 3 and 4 of present series got R-b's but were completely ignored by phy maintainers. Do you think it's fair if I resend these ones with a new, phy only, cover letter but keep the R-b tags? Thank you, Geraldo Nascimento
