Currently the PCIe OPP table is included entries for multiple lanes
configurations like x2. Since the driver now uses bw_factor to adjust
bandwidth based on link width, we only need to define OPPs for x1
lane configurations.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 17 ++---------------
1 file changed, 2 insertions(+), 15 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 54c6d0fdb2afa51084c510eddc341d6087189611..d752dc2b17f03284fada7584b5fbdf7672e06142 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -2216,20 +2216,13 @@ opp-2500000 {
opp-peak-kBps = <250000 1>;
};
- /* GEN 1 x2 and GEN 2 x1 */
+ /* GEN 2 x1 */
opp-5000000 {
opp-hz = /bits/ 64 <5000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <500000 1>;
};
- /* GEN 2 x2 */
- opp-10000000 {
- opp-hz = /bits/ 64 <10000000>;
- required-opps = <&rpmhpd_opp_low_svs>;
- opp-peak-kBps = <1000000 1>;
- };
-
/* GEN 3 x1 */
opp-8000000 {
opp-hz = /bits/ 64 <8000000>;
@@ -2237,19 +2230,13 @@ opp-8000000 {
opp-peak-kBps = <984500 1>;
};
- /* GEN 3 x2 and GEN 4 x1 */
+ /* GEN 4 x1 */
opp-16000000 {
opp-hz = /bits/ 64 <16000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <1969000 1>;
};
- /* GEN 4 x2 */
- opp-32000000 {
- opp-hz = /bits/ 64 <32000000>;
- required-opps = <&rpmhpd_opp_nom>;
- opp-peak-kBps = <3938000 1>;
- };
};
pcie@0 {
--
2.34.1
