On 7/16/2025 8:56 PM, Manivannan Sadhasivam via B4 Relay wrote:
> From: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxxxxxxxx>
>
> It is not recommended to enable/disable the ASPM states on the back of the
> PCI core directly using the LNKCTL register. It will break the PCI core's
> knowledge about the device ASPM states. So use the APIs exposed by the PCI
> core to enable/disable ASPM states.
>
> Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.0.c5-00481-QCAHMTSWPL_V1.0_V2.0_SILICONZ-3
>
> Reported-by: Qiang Yu <qiang.yu@xxxxxxxxxxxxxxxx>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxxxxxxxx>
> ---
> drivers/net/wireless/ath/ath.h | 14 ++++++++++++++
> drivers/net/wireless/ath/ath12k/pci.c | 10 ++++------
> 2 files changed, 18 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/net/wireless/ath/ath.h b/drivers/net/wireless/ath/ath.h
> index 34654f710d8a1e63f65a47d4602e2035262a4d9e..ef685123b66bf4f41428fec67c1967f242a9ef27 100644
> --- a/drivers/net/wireless/ath/ath.h
> +++ b/drivers/net/wireless/ath/ath.h
> @@ -21,6 +21,8 @@
> #include <linux/skbuff.h>
> #include <linux/if_ether.h>
> #include <linux/spinlock.h>
> +#include <linux/pci.h>
> +#include <linux/pci_regs.h>
> #include <net/mac80211.h>
>
> /*
> @@ -336,4 +338,16 @@ static inline const char *ath_bus_type_to_string(enum ath_bus_type bustype)
> return ath_bus_type_strings[bustype];
> }
>
> +static inline int ath_pci_aspm_state(u16 lnkctl)
> +{
> + int state = 0;
> +
> + if (lnkctl & PCI_EXP_LNKCTL_ASPM_L0S)
> + state |= PCIE_LINK_STATE_L0S;
> + if (lnkctl & PCI_EXP_LNKCTL_ASPM_L1)
> + state |= PCIE_LINK_STATE_L1;
> +
> + return state;
> +}
> +
> #endif /* ATH_H */
> diff --git a/drivers/net/wireless/ath/ath12k/pci.c b/drivers/net/wireless/ath/ath12k/pci.c
> index 489d546390fcdab8f615cc9184006a958d9f140a..a5e11509e3ab8faad6638ff78ce6a8a5e9c3cbbd 100644
> --- a/drivers/net/wireless/ath/ath12k/pci.c
> +++ b/drivers/net/wireless/ath/ath12k/pci.c
I add some logs:
diff --git a/drivers/net/wireless/ath/ath12k/pci.c b/drivers/net/wireless/ath/ath12k/pci.c
index de5a4059a7a9..5a52093e0226 100644
--- a/drivers/net/wireless/ath/ath12k/pci.c
+++ b/drivers/net/wireless/ath/ath12k/pci.c
@@ -1161,16 +1161,28 @@ void ath12k_pci_stop(struct ath12k_base *ab)
ath12k_ce_cleanup_pipes(ab);
}
+static void ath12k_pci_dump_pcie_link_ctrl(struct ath12k_pci *ab_pci, const char *str1,
u16 line)
+{
+ u16 link_ctl = 0;
+
+ pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL,
+ &link_ctl);
+
+ pr_info("%s %u: link_ctl 0x%x\n", str1, line, link_ctl);
+}
+
int ath12k_pci_start(struct ath12k_base *ab)
{
struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
set_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
+ ath12k_pci_dump_pcie_link_ctrl(ab_pci, __func__, __LINE__);
if (test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
ath12k_pci_aspm_restore(ab_pci);
else
ath12k_info(ab, "leaving PCI ASPM disabled to avoid MHI M2 problems\n");
+ ath12k_pci_dump_pcie_link_ctrl(ab_pci, __func__, __LINE__);
ath12k_pci_ce_irqs_enable(ab);
ath12k_ce_rx_post_buf(ab);
@@ -1460,11 +1472,15 @@ int ath12k_pci_power_up(struct ath12k_base *ab)
clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
ath12k_pci_sw_reset(ab_pci->ab, true);
+ ath12k_pci_dump_pcie_link_ctrl(ab_pci, __func__, __LINE__);
+
/* Disable ASPM during firmware download due to problems switching
* to AMSS state.
*/
ath12k_pci_aspm_disable(ab_pci);
+ ath12k_pci_dump_pcie_link_ctrl(ab_pci, __func__, __LINE__);
+
ath12k_pci_msi_enable(ab_pci);
if (ath12k_fw_feature_supported(ab, ATH12K_FW_FEATURE_MULTI_QRTR_ID))
> @@ -16,6 +16,8 @@
> #include "mhi.h"
> #include "debug.h"
>
> +#include "../ath.h"
> +
> #define ATH12K_PCI_BAR_NUM 0
> #define ATH12K_PCI_DMA_MASK 36
>
> @@ -928,8 +930,7 @@ static void ath12k_pci_aspm_disable(struct ath12k_pci *ab_pci)
> u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1));
>
> /* disable L0s and L1 */
> - pcie_capability_clear_word(ab_pci->pdev, PCI_EXP_LNKCTL,
> - PCI_EXP_LNKCTL_ASPMC);
> + pci_disable_link_state(ab_pci->pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
Not always, but sometimes seems the 'disable' does not work:
[ 279.920507] ath12k_pci_power_up 1475: link_ctl 0x43 //before disable
[ 279.920539] ath12k_pci_power_up 1482: link_ctl 0x43 //after disable
>
> set_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags);
> }
> @@ -958,10 +959,7 @@ static void ath12k_pci_aspm_restore(struct ath12k_pci *ab_pci)
> {
> if (ab_pci->ab->hw_params->supports_aspm &&
> test_and_clear_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags))
> - pcie_capability_clear_and_set_word(ab_pci->pdev, PCI_EXP_LNKCTL,
> - PCI_EXP_LNKCTL_ASPMC,
> - ab_pci->link_ctl &
> - PCI_EXP_LNKCTL_ASPMC);
> + pci_enable_link_state(ab_pci->pdev, ath_pci_aspm_state(ab_pci->link_ctl));
always, the 'enable' is not working:
[ 280.561762] ath12k_pci_start 1180: link_ctl 0x43 //before restore
[ 280.561809] ath12k_pci_start 1185: link_ctl 0x42 //after restore
> }
>
> static void ath12k_pci_cancel_workqueue(struct ath12k_base *ab)
>
In addition, frequently I can see below AER warnings:
[ 280.383143] aer_ratelimit: 30 callbacks suppressed
[ 280.383151] pcieport 0000:00:1c.0: AER: Correctable error message received from
0000:00:1c.0
[ 280.383177] pcieport 0000:00:1c.0: PCIe Bus Error: severity=Correctable, type=Data Link
Layer, (Transmitter ID)
[ 280.383184] pcieport 0000:00:1c.0: device [8086:7ab8] error status/mask=00001000/00002000
[ 280.383193] pcieport 0000:00:1c.0: [12] Timeout
