I have observed DPC setting LBMS and previous assertions of LBMS being carried into wait for secondary bus. When this happens it is possible for the link to be forced to 2.5GT/s if the EP is slow to enter link training. Waiting for secondary bus after clearing DPC status should give the link a "fresh start" from the perspective of LBMS tracking. Therefore DPC should reset LBMS state before clearing DPC status. Matthew W Carlis (1): PCI: Reset LBMS state before clearing DPC status. drivers/pci/pcie/dpc.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.46.0
