On Tue, Jul 1, 2025 at 4:26 PM Bjorn Helgaas <helgaas@xxxxxxxxxx> wrote:
>
> [+cc Rob]
>
> On Tue, Jul 01, 2025 at 01:21:29PM -0700, Mayank Rana wrote:
> > On 7/1/2025 9:52 AM, Bjorn Helgaas wrote:
> > > On Mon, Jun 16, 2025 at 03:42:58PM -0700, Mayank Rana wrote:
> > > > Document the required configuration to enable the PCIe root complex on
> > > > SA8255p, which is managed by firmware using power-domain based handling
> > > > and configured as ECAM compliant.
> > >
> > > > + soc {
> > > > + #address-cells = <2>;
> > > > + #size-cells = <2>;
> > > > +
> > > > + pci@1c00000 {
> > > > + compatible = "qcom,pcie-sa8255p";
> > > > + reg = <0x4 0x00000000 0 0x10000000>;
> > > > + device_type = "pci";
> > > > + #address-cells = <3>;
> > > > + #size-cells = <2>;
> > > > + ranges = <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff00000>,
> > > > + <0x43000000 0x4 0x10100000 0x4 0x10100000 0x0 0x40000000>;
> > > > + bus-range = <0x00 0xff>;
> > > > + dma-coherent;
> > > > + linux,pci-domain = <0>;
> > > > ...
> > >
> > > > + pcie@0 {
> > > > + device_type = "pci";
> > > > + reg = <0x0 0x0 0x0 0x0 0x0>;
> > > > + bus-range = <0x01 0xff>;
> > >
> > > This is a Root Port, right? Why do we need bus-range here? I assume
> > > that even without this, the PCI core can detect and manage the bus
> > > range using PCI_SECONDARY_BUS and PCI_SUBORDINATE_BUS.
> >
> > On Qualcomm SOCs, root complex based root host bridge is connected to single
> > PCIe bridge
> > with single root port. I have added bus-range based on discussion on this
> > thread https://lore.kernel.org/all/20240321-pcie-qcom-bridge-dts-
> > 2-0-1eb790c53e43@xxxxxxxxxx/
>
> I think you mean
> https://lore.kernel.org/all/20240321-pcie-qcom-bridge-dts-v2-0-1eb790c53e43@xxxxxxxxxx/
> so I assume you're looking at the conversation at
> https://lore.kernel.org/all/20250103210531.GA3252@bhelgaas/t/#u.
That's all misguided...
> So I guess the answer to my question is basically "to shut up DTC
> check":
It's possible DTC checks are wrong, I wrote them.
> Some DT for qcom,pcie-sa8255p might describe an Endpoint below this
> Root Port, and the Endpoint's 'reg' property includes a bus number
> determined by the Root Port configuration.
>
> DTC check validates the Endpoint's bus number by comparing it with
> the parent's 'bus-range', so it complains unless the Root Port
> includes a 'bus-range' property.
The complication here is how flattened DT works compared to
OpenFirmware. In OF, bus-range reflects how firmware assigned bus
numbers. In FDT, bus-range should only be present if there are
restrictions in bus numbers. So for most h/w, there should be no
bus-range properties anywhere. This also means the addressing should
just set the bus to 0 everywhere and only the devfn part is relevant.
Also note that the unit-addresses don't have the bus number so that
the device paths are consistent. The dtc check only says if the parent
has 'bus-range', then the address (reg) should have a bus number
within that range. There's never a warning that 'bus-range' is
missing.
Rob
