On Mon, Jul 14, 2025 at 10:43 PM Jacky Chou <jacky_chou@xxxxxxxxxxxxxx> wrote:
>
> The AST2600 has one PCIe RC, and add the relative configure regmap.
>
> Signed-off-by: Jacky Chou <jacky_chou@xxxxxxxxxxxxxx>
> ---
> arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 61 +++++++++++++++++++++++++
> 1 file changed, 61 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
> index 8ed715bd53aa..ed99780b6860 100644
> --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
> +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
> @@ -379,6 +379,67 @@ rng: hwrng@1e6e2524 {
> quality = <100>;
> };
>
> + pcie_phy1: syscon@1e6ed200 {
> + compatible = "aspeed,pcie-phy", "syscon";
> + reg = <0x1e6ed200 0x100>;
This looks like part of something else? It should be a child of that.
If this is the controls for the PCIe PHY, then use the PHY binding
instead of your own custom phandle property.
> + };
> +
> + pcie_cfg: syscon@1e770000 {
> + compatible = "aspeed,pcie-cfg", "syscon";
> + reg = <0x1e770000 0x80>;
Looks like this is really part of the PCIe block as a h/w block isn't
going to start at offset 0xc0.
> + };
> +
> + pcie0: pcie@1e7700c0 {
> + compatible = "aspeed,ast2600-pcie";
> + device_type = "pci";
> + reg = <0x1e7700c0 0x40>;
> + linux,pci-domain = <0>;
No need for this. You only have 1 PCI host.
> + #address-cells = <3>;
> + #size-cells = <2>;
> + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
> + bus-range = <0x80 0xff>;
Does this h/w not support bus 0-0x7f for some reason?
> +
> + ranges = <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000
> + 0x02000000 0x0 0x70000000 0x70000000 0x0 0x10000000>;
> +
> + status = "disabled";
> +
> + resets = <&syscon ASPEED_RESET_H2X>;
> + reset-names = "h2x";
> +
> + #interrupt-cells = <1>;
> + msi-parent = <&pcie0>;
> + msi-controller;
> +
> + aspeed,ahbc = <&ahbc>;
> + aspeed,pciecfg = <&pcie_cfg>;
> +
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie_intc0 0>,
> + <0 0 0 2 &pcie_intc0 1>,
> + <0 0 0 3 &pcie_intc0 2>,
> + <0 0 0 4 &pcie_intc0 3>;
> + pcie_intc0: interrupt-controller {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + };
> +
> + pcie@8,0 {
> + reg = <0x804000 0 0 0 0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + resets = <&syscon ASPEED_RESET_PCIE_RC_O>;
> + reset-names = "perst";
> + clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcierc1_default>;
> + aspeed,pciephy = <&pcie_phy1>;
> + ranges;
> + };
> + };
> +
> gfx: display@1e6e6000 {
> compatible = "aspeed,ast2600-gfx", "syscon";
> reg = <0x1e6e6000 0x1000>;
> --
> 2.43.0
>
