This series adds add equalization settings for 8.0 GT/s, and add PCIe lane equalization preset properties for 8.0 GT/s and 16.0 GT/s for sa8775p ride platform, which fix AER errors. While equalization settings for 16 GT/s have already been set, this update adds the required equalization settings for PCIe operating at 8.0 GT/s, including the configuration of shadow registers, ensuring optimal performance and stability. The DT change for sa8775p add PCIe lane equalization preset properties for 8 GT/s and 16 GT/s data rates used in lane equalization procedure. Signed-off-by: Ziyue Zhang <ziyue.zhang@xxxxxxxxxxxxxxxx> Changes in v4: - Bail out early if the link speed > 16 GT/s and use pci->max_link_speed directly (Mani) - Fix the build warning. (Bjorn) - Link to v3: https://lore.kernel.org/all/8ccd3731-8dbc-4972-a79a-ba78e90ec4a8@xxxxxxxxxxx/ Changes in v3: - Delte TODO tag and warn print in pcie-qcom-common.c. (Bjorn) - Refined the commit message for better readability. (Bjorn) - Link to v2: https://lore.kernel.org/all/20250611100319.464803-1-quic_ziyuzhan@xxxxxxxxxxx/ Changes in v2: - Update code in pcie-qcom-common.c make it easier to read. (Neil) - Fix the compile error. - Link to v1: https://lore.kernel.org/all/20250604091946.1890602-1-quic_ziyuzhan@xxxxxxxxxxx Ziyue Zhang (3): PCI: qcom: Add equalization settings for 8.0 GT/s PCI: qcom: fix macro typo for CURSOR arm64: dts: qcom: sa8775p: Add PCIe lane equalization preset properties arch/arm64/boot/dts/qcom/sa8775p.dtsi | 6 +++ drivers/pci/controller/dwc/pcie-designware.h | 5 +- drivers/pci/controller/dwc/pcie-qcom-common.c | 54 ++++++++++--------- drivers/pci/controller/dwc/pcie-qcom-common.h | 2 +- drivers/pci/controller/dwc/pcie-qcom-ep.c | 6 +-- drivers/pci/controller/dwc/pcie-qcom.c | 6 +-- 6 files changed, 45 insertions(+), 34 deletions(-) base-commit: 58ba80c4740212c29a1cf9b48f588e60a7612209 -- 2.34.1
