Sorry for so many individual reviews, but I've passed over this a few
times and had new questions/comments several times:
On Mon, Jul 07, 2025 at 11:48:39PM +0530, Manivannan Sadhasivam wrote:
> PERST# is an (optional) auxiliary signal provided by the PCIe host to
> components for signalling 'Fundamental Reset' as per the PCIe spec r6.0,
> sec 6.6.1.
> void pci_pwrctrl_init(struct pci_pwrctrl *pwrctrl, struct device *dev)
> {
> + struct pci_host_bridge *host_bridge = to_pci_host_bridge(dev->parent);
> + int devfn;
> +
> pwrctrl->dev = dev;
> INIT_WORK(&pwrctrl->work, rescan_work_func);
> +
> + if (!host_bridge->perst)
> + return;
> +
> + devfn = of_pci_get_devfn(dev_of_node(dev));
> + if (devfn >= 0 && host_bridge->perst[PCI_SLOT(devfn)])
This seems to imply a 1:1 correlation between slots and pwrctrl devices,
almost as if you expect everyone is using drivers/pci/pwrctrl/slot.c.
But there is also endpoint-specific pwrctrl support, and there's quite
a bit of flexibility around what these hierarchies can look like.
How do you account for that?
For example, couldn't you have both a "port" and an "endpoint" pwrctrl? Would
they both grab the same PERST# GPIO here? And might that incur excessive
resets, possibly even clobbering each other?
Or what if multiple slots are governed by a single GPIO? Do you expect
the bridge perst[] array to contain redundant GPIOs?
Brian
> + pwrctrl->perst = host_bridge->perst[PCI_SLOT(devfn)];
> }
> EXPORT_SYMBOL_GPL(pci_pwrctrl_init);
