On 7/10/2025 5:43 PM, Johan Hovold wrote:
On Fri, Jun 27, 2025 at 04:50:57PM +0200, Konrad Dybcio wrote:
On 6/25/25 11:00 AM, Ziyue Zhang wrote:
gcc_aux_clk is used in PCIe RC and it is not required in pcie phy, in
pcie phy it should be gcc_phy_aux_clk, so remove gcc_aux_clk and
replace it with gcc_phy_aux_clk.
GCC_PCIE_n_PHY_AUX_CLK is a downstream of the PHY's output..
are you sure the PHY should be **consuming** it too?
Could we get a reply here, please?
A bunch of Qualcomm SoCs in mainline do exactly this currently even
though it may not be correct (and some downstream dts do not use these
clocks).
Johan
Hi Johan
After reviewing the downstream platforms, it seems that GCC_PCIE_n_PHY_AUX_CLK
is generally needed. Would you mind letting us know if there are any platforms
where this clock is not required?
