On Mon, Jun 09, 2025 at 04:21:29PM GMT, Krishna Chaitanya Chundru wrote:
> QCOM PCIe controllers need to disable ASPM before initiating link
> re-train. So as part of pre_link_speed_change() disable ASPM and as
> part of post_link_speed_change() enable ASPM back.
>
> As the driver needs to enable the ASPM states that are enabled
> by the system, save PCI ASPM states before disabling them and
> in post_link_speed_change() use the saved ASPM states to enable
> back the ASPM.
>
> Update ICC & OPP votes based on the requested speed so that RPMh votes
> get updated based on the speed.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 63 ++++++++++++++++++++++++++++++++++
> 1 file changed, 63 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 02643579707f45fc7279023feb7dbc903e69822d..c4aa193bbdcc928603ae50e8d7029b152d62f977 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -276,10 +276,16 @@ struct qcom_pcie {
> struct dentry *debugfs;
> bool suspended;
> bool use_pm_opp;
> + int aspm_state; /* Store ASPM state used in pre & post link speed change */
> };
>
> #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
>
> +static void qcom_pcie_post_link_speed_change(struct pci_host_bridge *bridge,
> + struct pci_dev *pdev, int current_speed);
> +static int qcom_pcie_pre_link_speed_change(struct pci_host_bridge *bridge,
> + struct pci_dev *pdev, int current_speed);
> +
> static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
> {
> gpiod_set_value_cansleep(pcie->reset, 1);
> @@ -1263,6 +1269,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
> goto err_assert_reset;
> }
>
> + pp->bridge->pre_link_speed_change = qcom_pcie_pre_link_speed_change;
> + pp->bridge->post_link_speed_change = qcom_pcie_post_link_speed_change;
> return 0;
>
> err_assert_reset:
> @@ -1328,6 +1336,61 @@ static int qcom_pcie_set_icc_opp(struct qcom_pcie *pcie, int speed, int width)
> return ret;
> }
>
> +static int qcom_pcie_scale_bw(struct dw_pcie_rp *pp, int speed)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct qcom_pcie *pcie = to_qcom_pcie(pci);
> + u32 offset, status, width;
> +
> + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> + status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
> +
> + width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status);
> +
> + return qcom_pcie_set_icc_opp(pcie, speed, width);
> +}
> +
> +static void qcom_pcie_post_link_speed_change(struct pci_host_bridge *bridge,
> + struct pci_dev *pdev, int current_speed)
pdev is the 'port' isn't it?
- Mani
--
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