On Thu, Jul 03, 2025 at 12:25:12PM +0200, Lorenzo Pieralisi wrote: > An IRS supports Logical Peripheral Interrupts (LPIs) and implement > Linux IPIs on top of it. > > LPIs are used for interrupt signals that are translated by a > GICv5 ITS (Interrupt Translation Service) but also for software > generated IRQs - namely interrupts that are not driven by a HW > signal, ie IPIs. > > LPIs rely on memory storage for interrupt routing and state. > > LPIs state and routing information is kept in the Interrupt > State Table (IST). > > IRSes provide support for 1- or 2-level IST tables configured > to support a maximum number of interrupts that depend on the > OS configuration and the HW capabilities. > > On systems that provide 2-level IST support, always allow > the maximum number of LPIs; On systems with only 1-level > support, limit the number of LPIs to 2^12 to prevent > wasting memory (presumably a system that supports a 1-level > only IST is not expecting a large number of interrupts). > > On a 2-level IST system, L2 entries are allocated on > demand. > > The IST table memory is allocated using the kmalloc() interface; > the allocation required may be smaller than a page and must be > made up of contiguous physical pages if larger than a page. > > On systems where the IRS is not cache-coherent with the CPUs, > cache mainteinance operations are executed to clean and > invalidate the allocated memory to the point of coherency > making it visible to the IRS components. > > On GICv5 systems, IPIs are implemented using LPIs. > > Add an LPI IRQ domain and implement an IPI-specific IRQ domain created > as a child/subdomain of the LPI domain to allocate the required number > of LPIs needed to implement the IPIs. > > IPIs are backed by LPIs, add LPIs allocation/de-allocation > functions. > > The LPI INTID namespace is managed using an IDA to alloc/free LPI INTIDs. > > Associate an IPI irqchip with IPI IRQ descriptors to provide > core code with the irqchip.ipi_send_single() method required > to raise an IPI. > > Co-developed-by: Sascha Bischoff <sascha.bischoff@xxxxxxx> > Signed-off-by: Sascha Bischoff <sascha.bischoff@xxxxxxx> > Co-developed-by: Timothy Hayes <timothy.hayes@xxxxxxx> > Signed-off-by: Timothy Hayes <timothy.hayes@xxxxxxx> > Signed-off-by: Lorenzo Pieralisi <lpieralisi@xxxxxxxxxx> > Reviewed-by: Marc Zyngier <maz@xxxxxxxxxx> > Cc: Will Deacon <will@xxxxxxxxxx> > Cc: Thomas Gleixner <tglx@xxxxxxxxxxxxx> > Cc: Catalin Marinas <catalin.marinas@xxxxxxx> > Cc: Marc Zyngier <maz@xxxxxxxxxx> Acked-by: Catalin Marinas <catalin.marinas@xxxxxxx>
