On 6/18/2025 9:42 AM, Graham Whyte wrote: > > > On 6/16/2025 2:05 PM, Bjorn Helgaas wrote: >> On Mon, Jun 16, 2025 at 12:02:41PM -0700, Graham Whyte wrote: >>> On 6/13/2025 8:33 AM, Bjorn Helgaas wrote: >>>> On Thu, Jun 12, 2025 at 09:41:45AM -0700, Graham Whyte wrote: >>>>> On 6/11/2025 11:31 PM, Christoph Hellwig wrote: >>>>>> On Wed, Jun 11, 2025 at 01:08:21PM -0700, Graham Whyte wrote: >>>>>>> We can ask our HW engineers to implement function readiness but we need >>>>>>> to be able to support exiting products, hence why posting it as a quirk. >>>>>> >>>>>> Your report sounds like it works perfectly fine, it's just that you >>>>>> want to reduce the delay. For that you'll need to stick to the standard >>>>>> methods instead of adding quirks, which are for buggy hardware that does >>>>>> not otherwise work. >>>>> >>>>> Bjorn, what would you recommend as next steps here? >>>> >>>> This is a tough call and I don't pretend to have an obvious answer. I >>>> understand the desire to improve performance. On the other hand, PCI >>>> has been successful over the long term because devices adhere to >>>> standardized ways of doing things, which makes generic software >>>> possible. Quirks degrade that story, of course, especially when there >>>> is an existing standardized solution that isn't being used. I'm not >>>> at all happy about vendors that decide against the standard solution >>>> and then ask OS folks to do extra work to compensate. >>> >>> Should someone want to implement readiness time reporting down the road, >>> they'll need to do the same work as patch 1 in this series (making the >>> flr delay a configurable parameter). >> >> Sure. That's a trivial change. The problem is the quirk itself. >> >> The Readiness Time Reporting Extended Capability is read-only with no >> control bits in it so it requires no actual logic in the device. >> Maybe you can just implement that capability with a firmware change on >> the device and add the corresponding Linux support for it. > > Hi Bjorn, > > We checked with our HW folks, it's not possible for us to update the pci > register components with this particular card, they are read only. What > are your thoughts on the sysfs approach mentioned in the previous email? > > Thanks, > Graham Hi Bjorn, just wanted to follow up on this here.
