On Mon, 30 Jun 2025 19:24:15 -0300, Geraldo Nascimento wrote:
> During a 30-day debugging-run fighting quirky PCIe devices on RK3399
> some quality improvements began to take form and after feedback from
> community they reached more polished state.
>
> This will ensure maximum chance of retraining to 5.0GT/s, on all four
> lanes and fix async strobe TEST_WRITE disablement. On top of this,
> standard PCIe defines are now used to reference registers from offset
> at Capabilities Register.
>
> [...]
Applied, thanks!
[1/4] PCI: rockchip: Use standard PCIe defines
commit: a54fa9e656b38d64761478d06aa8679eae074ca1
[2/4] PCI: rockchip: Set Target Link Speed before retraining
commit: 7a886fbf4004a990cb7231d64370c622d0eb741f
Best regards,
--
Manivannan Sadhasivam <mani@xxxxxxxxxx>
