From: Hans Zhang <hans.zhang@xxxxxxxxxxx> Document the bindings for CIX Sky1 PCIe Controller configured in root complex mode with five root port. Supports 4 INTx, MSI and MSI-x interrupts from the ARM GICv3 controller. Signed-off-by: Hans Zhang <hans.zhang@xxxxxxxxxxx> Reviewed-by: Peter Chen <peter.chen@xxxxxxxxxxx> Reviewed-by: Manikandan K Pillai <mpillai@xxxxxxxxxxx> --- .../bindings/pci/cix,sky1-pcie-host.yaml | 133 ++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/cix,sky1-pcie-host.yaml diff --git a/Documentation/devicetree/bindings/pci/cix,sky1-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cix,sky1-pcie-host.yaml new file mode 100644 index 000000000000..b4395bc06f2f --- /dev/null +++ b/Documentation/devicetree/bindings/pci/cix,sky1-pcie-host.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/cix,sky1-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CIX Sky1 PCIe Root Complex + +maintainers: + - Hans Zhang <hans.zhang@xxxxxxxxxxx> + +description: + PCIe root complex controller based on the Cadence PCIe core. + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + - $ref: /schemas/pci/cdns-pcie.yaml# + +properties: + compatible: + oneOf: + - const: cix,sky1-pcie-host + + reg: + items: + - description: PCIe controller registers. + - description: Remote CIX System Unit registers. + - description: ECAM registers. + - description: Region for sending messages registers. + + reg-names: + items: + - const: reg + - const: rcsu + - const: cfg + - const: msg + + "#interrupt-cells": + const: 1 + + interrupt-map-mask: + items: + - const: 0 + - const: 0 + - const: 0 + - const: 7 + + interrupt-map: + maxItems: 4 + + max-link-speed: + maximum: 4 + + num-lanes: + maximum: 8 + + ranges: + maxItems: 3 + + msi-map: + maxItems: 1 + + vendor-id: + const: 0x1f6c + + device-id: + enum: + - 0x0001 + + cdns,no-inbound-bar: + description: | + Indicates the PCIe controller does not require an inbound BAR region. + type: boolean + + sky1,pcie-ctrl-id: + description: | + Specifies the PCIe controller instance identifier (0-4). + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 4 + +required: + - compatible + - reg + - reg-names + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map + - max-link-speed + - num-lanes + - bus-range + - device_type + - ranges + - msi-map + - vendor-id + - device-id + - cdns,no-inbound-bar + - sky1,pcie-ctrl-id + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + pcie_x8_rc: pcie@a010000 { + compatible = "cix,sky1-pcie-host"; + reg = <0x00 0x0a010000 0x00 0x10000>, + <0x00 0x0a000000 0x00 0x10000>, + <0x00 0x2c000000 0x00 0x4000000>, + <0x00 0x60000000 0x00 0x00100000>; + reg-names = "reg", "rcsu", "cfg", "msg"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH 0>; + max-link-speed = <4>; + num-lanes = <8>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0xc0 0xff>; + device_type = "pci"; + ranges = <0x01000000 0x00 0x60100000 0x00 0x60100000 0x00 0x00100000>, + <0x02000000 0x00 0x60200000 0x00 0x60200000 0x00 0x1fe00000>, + <0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>; + msi-map = <0xc000 &gic_its 0xc000 0x4000>; + vendor-id = <0x1f6c>; + device-id = <0x0001>; + sky1,pcie-ctrl-id = <0x0>; + cdns,no-inbound-bar; + }; -- 2.49.0
