On Mon, Jun 23, 2025 at 02:00:57PM +0200, AngeloGioacchino Del Regno wrote: > Add compatible strings for MT8196 and MT6991 (which are fully > compatible between each other) and clock definitions. > > These new SoCs don't have tl_96m and tl_32k clocks, but need > an AHB to APB bus clock and a low power clock. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx> > --- > .../bindings/pci/mediatek-pcie-gen3.yaml | 35 +++++++++++++++++++ > 1 file changed, 35 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > index 162406e0691a..02cddf0246ce 100644 > --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > @@ -52,7 +52,12 @@ properties: > - mediatek,mt8188-pcie > - mediatek,mt8195-pcie > - const: mediatek,mt8192-pcie > + - items: > + - enum: > + - mediatek,mt6991-pcie > + - const: mediatek,mt8196-pcie > - const: mediatek,mt8192-pcie > + - const: mediatek,mt8196-pcie > - const: airoha,en7581-pcie > > reg: > @@ -212,6 +217,36 @@ allOf: > > mediatek,pbus-csr: false > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - mediatek,mt8196-pcie > + then: > + properties: > + clocks: > + minItems: 6 > + > + clock-names: > + items: > + - const: pl_250m > + - const: tl_26m > + - const: bus > + - const: low_power > + - const: peri_26m > + - const: peri_mem > + > + resets: > + minItems: 1 The min is already 1. > + maxItems: 2 > + > + reset-names: > + minItems: 1 > + maxItems: 2 It would be good to define what the names are. I assume they are fixed and not just any of the allowed ones. > + > + mediatek,pbus-csr: false > + > - if: > properties: > compatible: > -- > 2.49.0 >
