On Thu, 26 Jun 2025 17:42:44 -0500
Terry Bowman <terry.bowman@xxxxxxx> wrote:
> CXL Endpoint (EP) Ports may include Root Ports (RP) or Downstream Switch
> Ports (DSP). CXL RPs and DSPs contain RAS registers that require memory
> mapping to enable RAS logging. This initialization is currently missing and
> must be added for CXL RPs and DSPs.
>
> Update cxl_dport_init_ras_reporting() to support RP and DSP RAS mapping.
> Add alongside the existing Restricted CXL Host Downstream Port RAS mapping.
>
> Update cxl_endpoint_port_probe() to invoke cxl_dport_init_ras_reporting().
> This will initiate the RAS mapping for CXL RPs and DSPs when each CXL EP is
> created and added to the EP port.
>
> Signed-off-by: Terry Bowman <terry.bowman@xxxxxxx>
One trivial comment inline. I'm not super confident that I follow exactly
what is going on here so more eyes needed. However I think it's fine.
Reviewed-by: Jonathan Cameron <jonathan.cameron@xxxxxxxxxx>
> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> index 021f35145c65..b52f82925891 100644
> --- a/drivers/cxl/port.c
> +++ b/drivers/cxl/port.c
>
> +static void cxl_switch_port_init_ras(struct cxl_port *port)
> +{
> + if (is_cxl_root(to_cxl_port(port->dev.parent)))
> + return;
> +
> + /* May have upstream DSP or RP */
> + if (port->parent_dport && dev_is_pci(port->parent_dport->dport_dev)) {
A lot of port->parent_dport in here. Maybe a local variable for that with
a suitable name to describe that its the next port in the upstream direction.
> + struct pci_dev *pdev = to_pci_dev(port->parent_dport->dport_dev);
> +
> + if ((pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) ||
> + (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM))
> + cxl_dport_init_ras_reporting(port->parent_dport, &port->dev);
> + }
> +
> + cxl_uport_init_ras_reporting(port, &port->dev);
> +}
> +
> +static void cxl_endpoint_port_init_ras(struct cxl_port *port)
> +{
> + struct cxl_dport *dport;
> + struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);
> + struct cxl_port *parent_port __free(put_cxl_port) =
> + cxl_mem_find_port(cxlmd, &dport);
> +
> + if (!dport || !dev_is_pci(dport->dport_dev)) {
> + dev_err(&port->dev, "CXL port topology not found\n");
> + return;
> + }
> +
> + cxl_dport_init_ras_reporting(dport, cxlmd->cxlds->dev);
> +}
>
