On Thu, 26 Jun 2025 17:42:43 -0500
Terry Bowman <terry.bowman@xxxxxxx> wrote:
> The cxl_port driver is intended to manage CXL Endpoint Ports and CXL Switch
> Ports. Move existing RAS initialization to the cxl_port driver.
>
> Restricted CXL Host (RCH) Downstream Port RAS initialization currently
> resides in cxl/core/pci.c. The PCI source file is not otherwise associated
> with CXL Port management.
>
> Additional CXL Port RAS initialization will be added in future patches to
> support a CXL Port device's CXL errors.
>
> Signed-off-by: Terry Bowman <terry.bowman@xxxxxxx>
One small thing inline.
Reviewed-by: Jonathan Cameron <jonathan.cameron@xxxxxxxxxx>
> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> index fe4b593331da..021f35145c65 100644
> --- a/drivers/cxl/port.c
> +++ b/drivers/cxl/port.c
> @@ -6,6 +6,7 @@
> +
> +static void cxl_disable_rch_root_ints(struct cxl_dport *dport)
> +{
> + void __iomem *aer_base = dport->regs.dport_aer;
> + u32 aer_cmd_mask, aer_cmd;
> +
> + if (!aer_base)
> + return;
> +
> + /*
> + * Disable RCH root port command interrupts.
> + * CXL 3.2 12.2.1.1 - RCH Downstream Port-detected Errors
Don't update spec versions in a code move patch. That's a separate change
appropriate for doing in a separate patch.
For this we just want to see code moved with zero changes at all.
> + *
> + * This sequence may not be necessary. CXL spec states disabling
> + * the root cmd register's interrupts is required. But, PCI spec
> + * shows these are disabled by default on reset.
> + */
> + aer_cmd_mask = (PCI_ERR_ROOT_CMD_COR_EN |
> + PCI_ERR_ROOT_CMD_NONFATAL_EN |
> + PCI_ERR_ROOT_CMD_FATAL_EN);
> + aer_cmd = readl(aer_base + PCI_ERR_ROOT_COMMAND);
> + aer_cmd &= ~aer_cmd_mask;
> + writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND);
> +}
> +
