On Wed, Jun 11, 2025 at 06:03:19PM +0800, Ziyue Zhang wrote:
> Add PCIe lane equalization preset properties with all values set to 5 for
> 8.0 GT/s and 16.0 GT/s data rates to enhance link stability.
>
> Co-developed-by: Qiang Yu <qiang.yu@xxxxxxxxxxxxxxxx>
> Signed-off-by: Qiang Yu <qiang.yu@xxxxxxxxxxxxxxxx>
> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@xxxxxxxxxxx>
Acked-by: Manivannan Sadhasivam <mani@xxxxxxxxxx>
- Mani
> ---
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index 45f536633f64..16caf1da0708 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -7159,6 +7159,9 @@ pcie0: pcie@1c00000 {
> phys = <&pcie0_phy>;
> phy-names = "pciephy";
>
> + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
> + eq-presets-16gts = /bits/ 8 <0x55 0x55>;
> +
> status = "disabled";
>
> pcieport0: pcie@0 {
> @@ -7317,6 +7320,9 @@ pcie1: pcie@1c10000 {
> phys = <&pcie1_phy>;
> phy-names = "pciephy";
>
> + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
> + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
> +
> status = "disabled";
>
> pcie@0 {
> --
> 2.34.1
>
--
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