On Fri, Jun 13, 2025 at 02:48:41PM +0200, Niklas Cassel wrote:
> Macro PCIE_RESET_CONFIG_WAIT_MS was added to pci.h in commit d5ceb9496c56
s/PCIE_RESET_CONFIG_WAIT_MS/PCIE_RESET_CONFIG_DEVICE_WAIT_MS
> ("PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time value").
>
> Later, in commit 70a7bfb1e515 ("PCI: rockchip-host: Wait 100ms after reset
> before starting configuration"), PCIE_T_RRS_READY_MS was added to pci.h.
>
> These macros are duplicates, and represent the exact same delay in the
> PCIe specification.
>
> Since the comment above PCIE_RESET_CONFIG_WAIT_MS is strictly more correct
> than the comment above PCIE_T_RRS_READY_MS, change rockchip-host to use
> PCIE_RESET_CONFIG_WAIT_MS, and remove PCIE_T_RRS_READY_MS, as
> rockchip-host is the only user of this macro.
>
> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@xxxxxxx>
> Signed-off-by: Niklas Cassel <cassel@xxxxxxxxxx>
LGTM!
- Mani
> ---
> drivers/pci/controller/pcie-rockchip-host.c | 2 +-
> drivers/pci/pci.h | 7 -------
> 2 files changed, 1 insertion(+), 8 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c
> index b9e7a8710cf0..c11ed45c25f6 100644
> --- a/drivers/pci/controller/pcie-rockchip-host.c
> +++ b/drivers/pci/controller/pcie-rockchip-host.c
> @@ -325,7 +325,7 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)
> msleep(PCIE_T_PVPERL_MS);
> gpiod_set_value_cansleep(rockchip->perst_gpio, 1);
>
> - msleep(PCIE_T_RRS_READY_MS);
> + msleep(PCIE_RESET_CONFIG_WAIT_MS);
>
> /* 500ms timeout value should be enough for Gen1/2 training */
> err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> index 98d6fccb383e..819833e57590 100644
> --- a/drivers/pci/pci.h
> +++ b/drivers/pci/pci.h
> @@ -35,13 +35,6 @@ struct pcie_tlp_log;
> */
> #define PCIE_T_PERST_CLK_US 100
>
> -/*
> - * End of conventional reset (PERST# de-asserted) to first configuration
> - * request (device able to respond with a "Request Retry Status" completion),
> - * from PCIe r6.0, sec 6.6.1.
> - */
> -#define PCIE_T_RRS_READY_MS 100
> -
> /*
> * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>
> * Recommends 1ms to 10ms timeout to check L2 ready.
> --
> 2.49.0
>
--
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