During a 30-day debugging-run fighting quirky PCIe devices on RK3399 some quality improvements began to take form and this is my attempt at upstreaming it. It will ensure maximum chance of retraining to Gen2 5.0GT/s, on all four lanes and fix async strobe TEST_WRITE disablement. --- V5 -> V6: reflow to 75 cols, use 5.0GTs instead of Gen2 nomenclature, clarify strobe write adjustment and remove PHY_CFG_RD_MASK V4 -> V5: fix build failure, reflow commit messages and also convert registers for EP operation, all suggested by Ilpo V3 -> V4: fix setting-up of TLS in Link Control and Status Register 2, also adjust commit titles V2 -> V3: correctly clean-up with standard PCIe defines as per Bjorn's suggestion V1 -> V2: use standard PCIe defines as suggested by Bjorn Geraldo Nascimento (4): PCI: rockchip: Use standard PCIe defines PCI: rockchip: Set Target Link Speed before retraining phy: rockchip-pcie: Enable all four lanes if required phy: rockchip-pcie: Properly disable TEST_WRITE strobe signal drivers/pci/controller/pcie-rockchip-ep.c | 4 +- drivers/pci/controller/pcie-rockchip-host.c | 48 +++++++++++---------- drivers/pci/controller/pcie-rockchip.h | 12 +----- drivers/phy/rockchip/phy-rockchip-pcie.c | 15 +++---- 4 files changed, 36 insertions(+), 43 deletions(-) -- 2.49.0
