On Fri, Jun 20, 2025 at 01:04:46PM +0100, Robin Murphy wrote: > On 2025-06-13 6:03 pm, Geraldo Nascimento wrote: > > Current code enables only Lane 0 because pwr_cnt will be incremented > > on first call to the function. Use for-loop to enable all 4 lanes > > through GRF. > > If this was really necessary, then surely it would also need the > equivalent changes in rockchip_pcie_phy_power_off() too? > > However, I'm not sure it *is* necessary - the NVMe on my RK3399 board > happily claims to be using an x4 link, so I stuck a print of inst->index > in this function, and sure enough I do see it being called for each > instance already: > > [ 1.737479] phy phy-ff770000.syscon:pcie-phy.1: power_on 0 > [ 1.738810] phy phy-ff770000.syscon:pcie-phy.2: power_on 1 > [ 1.745193] phy phy-ff770000.syscon:pcie-phy.3: power_on 2 > [ 1.745196] phy phy-ff770000.syscon:pcie-phy.4: power_on 3 > Hi Robin, and thanks for caring, it's excellent to rely on your extensive expertise on ARM in general and RK3399 specifically! However, on my board I'm positive it does not work without proposed patch and I get stuck with x1 link without it. There are currently very similar patches applied downstream to Armbian and OpenWRT so at least I'm confident that is not only my board which is quirky and other people experienced the same problem. Thanks, Geraldo Nascimento > Thanks, > Robin.
