On Wed, Jun 18, 2025 at 10:41:14AM +0800, Richard Zhu wrote:
> Refer to PCIe r6.0, sec 5.2, fig 5-1 Link Power Management State Flow
> Diagram. Both L0 and L2/L3 Ready can be transferred to LDn directly.
>
> It's harmless to let dw_pcie_suspend_noirq() proceed suspend after the
> PME_Turn_Off is sent out, whatever the LTSSM state is in L2 or L3 after
> a recommended 10ms max wait refer to PCIe r6.0, sec 5.3.3.2.1 PME
> Synchronization.
>
> The LTSSM states are inaccessible on i.MX6QP, and i.MX7D after the
^ needn't ,
> PME_Turn_Off is sent out.
>
> To handle this case, don't poll L2 state and add one max 10ms delay if
> QUIRK_NOL2POLL_IN_PM flag is existing in suspend.
To support this case, don't poll L2 state and apply a simple delay of
PCIE_PME_TO_L2_TIMEOUT_US(10ms) if the QUIRK_NOL2POLL_IN_PM flag is set in
suspend.
Reviewed-by: Frank Li <Frank.Li@xxxxxxx>
>
> Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
> ---
> .../pci/controller/dwc/pcie-designware-host.c | 31 +++++++++++++------
> drivers/pci/controller/dwc/pcie-designware.h | 4 +++
> 2 files changed, 25 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 906277f9ffaf..2d58a3eb94a1 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -1026,7 +1026,7 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci)
> {
> u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> u32 val;
> - int ret;
> + int ret = 0;
>
> /*
> * If L1SS is supported, then do not put the link into L2 as some
> @@ -1043,15 +1043,26 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci)
> return ret;
> }
>
> - ret = read_poll_timeout(dw_pcie_get_ltssm, val,
> - val == DW_PCIE_LTSSM_L2_IDLE ||
> - val <= DW_PCIE_LTSSM_DETECT_WAIT,
> - PCIE_PME_TO_L2_TIMEOUT_US/10,
> - PCIE_PME_TO_L2_TIMEOUT_US, false, pci);
> - if (ret) {
> - /* Only log message when LTSSM isn't in DETECT or POLL */
> - dev_err(pci->dev, "Timeout waiting for L2 entry! LTSSM: 0x%x\n", val);
> - return ret;
> + if (dwc_quirk(pci, QUIRK_NOL2POLL_IN_PM)) {
> + /*
> + * Refer to PCIe r6.0, sec 5.2, fig 5-1 Link Power Management
> + * State Flow Diagram. Both L0 and L2/L3 Ready can be
> + * transferred to LDn directly. On the LTSSM states poll broken
> + * platforms, add a max 10ms delay refer to PCIe r6.0,
> + * sec 5.3.3.2.1 PME Synchronization.
> + */
> + mdelay(PCIE_PME_TO_L2_TIMEOUT_US/1000);
> + } else {
> + ret = read_poll_timeout(dw_pcie_get_ltssm, val,
> + val == DW_PCIE_LTSSM_L2_IDLE ||
> + val <= DW_PCIE_LTSSM_DETECT_WAIT,
> + PCIE_PME_TO_L2_TIMEOUT_US/10,
> + PCIE_PME_TO_L2_TIMEOUT_US, false, pci);
> + if (ret) {
> + /* Only log message when LTSSM isn't in DETECT or POLL */
> + dev_err(pci->dev, "Timeout waiting for L2 entry! LTSSM: 0x%x\n", val);
> + return ret;
> + }
> }
>
> /*
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index ce9e18554e42..e35b19cbd8bf 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -299,6 +299,9 @@
> /* Default eDMA LLP memory size */
> #define DMA_LLP_MEM_SIZE PAGE_SIZE
>
> +#define QUIRK_NOL2POLL_IN_PM BIT(0)
> +#define dwc_quirk(pci, val) (pci->quirk_flag & val)
> +
> struct dw_pcie;
> struct dw_pcie_rp;
> struct dw_pcie_ep;
> @@ -509,6 +512,7 @@ struct dw_pcie {
> const struct dw_pcie_ops *ops;
> u32 version;
> u32 type;
> + u32 quirk_flag;
> unsigned long caps;
> int num_lanes;
> int max_link_speed;
> --
> 2.37.1
>
