Maybe you also want to allow the EFP ->link_down() callbacks to also
program things via DBI before link training? But I don't think the
amount of time they take is relevant. If you need to do *anything*
via DBI before the link trains, you have to prevent training until
you're finished with DBI.
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@xxxxxxx>
> Co-developed-by: Niklas Cassel <cassel@xxxxxxxxxx>
> Signed-off-by: Niklas Cassel <cassel@xxxxxxxxxx>
> ---
> Changes since v1:
> -Rebased on v6.16-rc1
>
> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 15 ++++++++++++---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> index 93171a392879..cd1e9352b21f 100644
> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> @@ -58,6 +58,8 @@
>
> /* Hot Reset Control Register */
> #define PCIE_CLIENT_HOT_RESET_CTRL 0x180
> +#define PCIE_LTSSM_APP_DLY2_EN BIT(1)
> +#define PCIE_LTSSM_APP_DLY2_DONE BIT(3)
> #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
>
> /* LTSSM Status Register */
> @@ -474,7 +476,7 @@ static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg)
> struct rockchip_pcie *rockchip = arg;
> struct dw_pcie *pci = &rockchip->pci;
> struct device *dev = pci->dev;
> - u32 reg;
> + u32 reg, val;
>
> reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC);
> rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);
> @@ -485,6 +487,10 @@ static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg)
> if (reg & PCIE_LINK_REQ_RST_NOT_INT) {
> dev_dbg(dev, "hot reset or link-down reset\n");
> dw_pcie_ep_linkdown(&pci->ep);
> + /* Stop delaying link training. */
> + val = HIWORD_UPDATE_BIT(PCIE_LTSSM_APP_DLY2_DONE);
> + rockchip_pcie_writel_apb(rockchip, val,
> + PCIE_CLIENT_HOT_RESET_CTRL);
> }
>
> if (reg & PCIE_RDLH_LINK_UP_CHGED) {
> @@ -566,8 +572,11 @@ static int rockchip_pcie_configure_ep(struct platform_device *pdev,
> return ret;
> }
>
> - /* LTSSM enable control mode */
> - val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
> + /*
> + * LTSSM enable control mode, and automatically delay link training on
> + * hot reset/link-down reset.
> + */
> + val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE | PCIE_LTSSM_APP_DLY2_EN);
> rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
>
> rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_EP_MODE,
> --
> 2.49.0
>
