On Thu, May 29, 2025 at 10:10:24AM +0800, Hans Zhang wrote: > Update the device tree binding documentation for PCI to include > PCIe Gen5 and Gen6 support in the `max-link-speed` property. > The original documentation limited the value to 1~4 (Gen1~Gen4), > but the kernel now supports up to Gen6. This change ensures the > documentation aligns with the actual code implementation. > > Signed-off-by: Hans Zhang <18255117159@xxxxxxx> > --- > dtschema/schemas/pci/pci-bus-common.yaml | 2 +- As Rob commented in v1, this file lives in dtschema project. So update it there: https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/pci/pci-bus-common.yaml - Mani > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/dtschema/schemas/pci/pci-bus-common.yaml b/dtschema/schemas/pci/pci-bus-common.yaml > index ca97a00..413ef05 100644 > --- a/dtschema/schemas/pci/pci-bus-common.yaml > +++ b/dtschema/schemas/pci/pci-bus-common.yaml > @@ -121,7 +121,7 @@ properties: > unnecessary operation for unsupported link speed, for instance, trying to > do training for unsupported link speed, etc. > $ref: /schemas/types.yaml#/definitions/uint32 > - enum: [ 1, 2, 3, 4 ] > + enum: [ 1, 2, 3, 4, 5, 6 ] > > num-lanes: > description: The number of PCIe lanes > -- > 2.25.1 > -- மணிவண்ணன் சதாசிவம்
