This series drop gcc_aux_clock in pcie phy, the pcie aux clock should be gcc_phy_aux_clock. And sa8775p platform support link_down reset in hardware, so add it for both pcie0 and pcie1 to provide a better user experience. Have follwing changes: - Update pcie phy bindings for sa8775p. - Document link_down reset. - Remove aux clock from pcie phy. - Add link_down reset for pcie. Signed-off-by: Ziyue Zhang <quic_ziyuzhan@xxxxxxxxxxx> Changes in v2: - Change link_down reset from optional to mandatory(Konrad) - Link to v1: https://lore.kernel.org/all/20250529035416.4159963-1-quic_ziyuzhan@xxxxxxxxxxx/ Ziyue Zhang (4): dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings for sa8775p dt-bindings: PCI: qcom,pcie-sa8775p: document link_down reset arm64: dts: qcom: sa8775p: remove aux clock from pcie phy arm64: dts: qcom: sa8775p: add link_down reset for pcie .../bindings/pci/qcom,pcie-sa8775p.yaml | 13 ++++-- .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 4 +- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 42 ++++++++++++------- 3 files changed, 37 insertions(+), 22 deletions(-) base-commit: 4f27f06ec12190c7c62c722e99ab6243dea81a94 -- 2.34.1
