On 6/13/2025 8:33 AM, Bjorn Helgaas wrote: > On Thu, Jun 12, 2025 at 09:41:45AM -0700, Graham Whyte wrote: >> On 6/11/2025 11:31 PM, Christoph Hellwig wrote: >>> On Wed, Jun 11, 2025 at 01:08:21PM -0700, Graham Whyte wrote: >>>> We can ask our HW engineers to implement function readiness but we need >>>> to be able to support exiting products, hence why posting it as a quirk. >>> >>> Your report sounds like it works perfectly fine, it's just that you >>> want to reduce the delay. For that you'll need to stick to the standard >>> methods instead of adding quirks, which are for buggy hardware that does >>> not otherwise work. >> >> Bjorn, what would you recommend as next steps here? > > This is a tough call and I don't pretend to have an obvious answer. I > understand the desire to improve performance. On the other hand, PCI > has been successful over the long term because devices adhere to > standardized ways of doing things, which makes generic software > possible. Quirks degrade that story, of course, especially when there > is an existing standardized solution that isn't being used. I'm not > at all happy about vendors that decide against the standard solution > and then ask OS folks to do extra work to compensate. > > Bjorn Hi Bjorn, Should someone want to implement readiness time reporting down the road, they'll need to do the same work as patch 1 in this series (making the flr delay a configurable parameter). This change lays the groundwork for that work, while also supporting devices that can't use readiness time reporting. Alternatively could we use a sysfs file to make this parameter configurable via the user space application? Similar to switching between d3hot and d3cold by writing to /sys/bus/pci/slots/$DEVICE/power. Thanks, Graham
