On Fri, Jun 13, 2025 at 02:03:50PM -0300, Geraldo Nascimento wrote: > Current code may fail Gen2 retraining if Target Link Speed > is set to 2.5 GT/s in Link Control and Status Register 2. > Set it to 5.0 GT/s accordingly. > > Signed-off-by: Geraldo Nascimento <geraldogabriel@xxxxxxxxx> > --- > drivers/pci/controller/pcie-rockchip-host.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c > index 8489d51e01ca..467e3fc377f7 100644 > --- a/drivers/pci/controller/pcie-rockchip-host.c > +++ b/drivers/pci/controller/pcie-rockchip-host.c > @@ -341,6 +341,10 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip) > * Enable retrain for gen2. This should be configured only after > * gen1 finished. > */ > + status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2); > + status &= ~PCI_EXP_LNKCTL2_TLS; > + status |= PCI_EXP_LNKCTL2_TLS_5_0GT; > + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2); > rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2); Hi, I see rockchip_pcie_write() was added twice, in this patch and also in 1/4. I'll send v6 with correction after I get some reviews. Thank you, Geraldo Nascimento > status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); > status |= PCI_EXP_LNKCTL_RL; > -- > 2.49.0 >
