On Thu, May 22, 2025 at 02:39:59PM +0200, Niklas Cassel wrote:
> From: Wilfred Mallawa <wilfred.mallawa@xxxxxxx>
>
> RK3588 TRM, section "11.6.1.3.3 Hot Reset and Link-Down Reset" states that:
> """
> If you want to delay link re-establishment (after reset) so that you can
> reprogram some registers through DBI, you must set app_ltssm_enable =0
> immediately after core_rst_n as shown in above. This can be achieved by
> enable the app_dly2_en, and end-up the delay by assert app_dly2_done.
> """
>
> I.e. setting app_dly2_en will automatically deassert app_ltssm_enable on
> a hot reset, and setting app_dly2_done will re-assert app_ltssm_enable,
> re-enabling link training.
>
> When receiving a hot reset/link-down IRQ when running in EP mode, we will
> call dw_pcie_ep_linkdown(), which will call the .link_down() callback in
> the currently bound endpoint function (EPF) drivers.
>
> The callback in an EPF driver can theoretically take a long time to
> complete, so make sure that the link is not re-established until after
> dw_pcie_ep_linkdown() (which calls the .link_down() callback(s)
> synchronously).
>
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@xxxxxxx>
> Co-developed-by: Niklas Cassel <cassel@xxxxxxxxxx>
> Signed-off-by: Niklas Cassel <cassel@xxxxxxxxxx>
This patch is not applying on top of v6.16-rc1. Please post it after rebasing.
- Mani
> ---
> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 15 ++++++++++++---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> index c4bd7e0abdf0..05b8e4cbd30b 100644
> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> @@ -61,6 +61,8 @@
>
> /* Hot Reset Control Register */
> #define PCIE_CLIENT_HOT_RESET_CTRL 0x180
> +#define PCIE_LTSSM_APP_DLY2_EN BIT(1)
> +#define PCIE_LTSSM_APP_DLY2_DONE BIT(3)
> #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
>
> /* LTSSM Status Register */
> @@ -487,7 +489,7 @@ static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg)
> struct rockchip_pcie *rockchip = arg;
> struct dw_pcie *pci = &rockchip->pci;
> struct device *dev = pci->dev;
> - u32 reg;
> + u32 reg, val;
>
> reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC);
> rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);
> @@ -498,6 +500,10 @@ static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg)
> if (reg & PCIE_LINK_REQ_RST_NOT_INT) {
> dev_dbg(dev, "hot reset or link-down reset\n");
> dw_pcie_ep_linkdown(&pci->ep);
> + /* Stop delaying link training. */
> + val = HIWORD_UPDATE_BIT(PCIE_LTSSM_APP_DLY2_DONE);
> + rockchip_pcie_writel_apb(rockchip, val,
> + PCIE_CLIENT_HOT_RESET_CTRL);
> }
>
> if (reg & PCIE_RDLH_LINK_UP_CHGED) {
> @@ -585,8 +591,11 @@ static int rockchip_pcie_configure_ep(struct platform_device *pdev,
> return ret;
> }
>
> - /* LTSSM enable control mode */
> - val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
> + /*
> + * LTSSM enable control mode, and automatically delay link training on
> + * hot reset/link-down reset.
> + */
> + val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE | PCIE_LTSSM_APP_DLY2_EN);
> rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
>
> /*
> --
> 2.49.0
>
--
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