On Thu, May 15, 2025 at 02:35:17PM +0530, Krishna Chaitanya Chundru wrote:
> As per PCIe spec 6, sec 5.3.3.2 document PCI standard WAKE# signal,
> which is used to re-establish power and reference clocks to the
> components within its domain.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx>
> ---
> dtschema/schemas/pci/pci-bus-common.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/dtschema/schemas/pci/pci-bus-common.yaml b/dtschema/schemas/pci/pci-bus-common.yaml
> index ca97a00..a39fafc 100644
> --- a/dtschema/schemas/pci/pci-bus-common.yaml
> +++ b/dtschema/schemas/pci/pci-bus-common.yaml
> @@ -142,6 +142,10 @@ properties:
> description: GPIO controlled connection to PERST# signal
> maxItems: 1
>
> + wake-gpios:
> + description: GPIO controlled connection to WAKE# signal
"GPIO controlled" makes it sound like the GPIO can assert or deassert
the WAKE# signal. But isn't WAKE# driven ("controlled") by a PCIe
endpoint, and this GPIO would be input-only at the other end to sense
the state of WAKE#?
