On Fri, Jun 06, 2025 at 09:57:38AM +0800, Macpaul Lin wrote: > From: Ajay Agarwal <ajayagarwal@xxxxxxxxxx> > > [ Upstream commit 7447990137bf06b2aeecad9c6081e01a9f47f2aa ] > > PCIe r6.2, sec 5.5.4, requires that: > > If setting either or both of the enable bits for ASPM L1 PM Substates, > both ports must be configured as described in this section while ASPM L1 > is disabled. > > Previously, pcie_config_aspm_l1ss() assumed that "setting enable bits" > meant "setting them to 1", and it configured L1SS as follows: > > - Clear L1SS enable bits > - Disable L1 > - Configure L1SS enable bits as required > - Enable L1 if required > > With this sequence, when disabling L1SS on an ARM A-core with a Synopsys > DesignWare PCIe core, the CPU occasionally hangs when reading > PCI_L1SS_CTL1, leading to a reboot when the CPU watchdog expires. > > Move the L1 disable to the caller (pcie_config_aspm_link(), where L1 was > already enabled) so L1 is always disabled while updating the L1SS bits: > > - Disable L1 > - Clear L1SS enable bits > - Configure L1SS enable bits as required > - Enable L1 if required > > Change pcie_aspm_cap_init() similarly. > > Link: https://lore.kernel.org/r/20241007032917.872262-1-ajayagarwal@xxxxxxxxxx > Signed-off-by: Ajay Agarwal <ajayagarwal@xxxxxxxxxx> > [bhelgaas: comments, commit log, compute L1SS setting before config access] > Signed-off-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx> > Tested-by: Johnny-CC Chang <Johnny-CC.Chang@xxxxxxxxxxxx> > Signed-off-by: Macpaul Lin <macpaul.lin@xxxxxxxxxxxx> > --- > drivers/pci/pcie/aspm.c | 92 ++++++++++++++++++++++------------------- > 1 file changed, 50 insertions(+), 42 deletions(-) 6.11.y is long end-of-life, sorry. See the front page of www.kernel.org for the list of currently supported kernels. thanks, greg k-h
