On 6/6/2025 12:04 PM, Dave Jiang wrote:
>
> On 6/3/25 10:22 AM, Terry Bowman wrote:
>> The cxl_port driver is intended to manage CXL Endpoint Ports and CXL Switch
>> Ports. Move existing RAS initialization to the cxl_port driver.
>>
>> Restricted CXL Host (RCH) Downstream Port RAS initialization currently
>> resides in cxl/core/pci.c. The PCI source file is not otherwise associated
>> with CXL Port management.
>>
>> Additional CXL Port RAS initialization will be added in future patches to
>> support a CXL Port device's CXL errors.
> Is this the part that Jonathan recommended moving to cxl/core/ras.c?
>
> DJ
Correct.
Terry
>> Signed-off-by: Terry Bowman <terry.bowman@xxxxxxx>
>> ---
>> drivers/cxl/core/pci.c | 73 --------------------------------------
>> drivers/cxl/core/regs.c | 2 ++
>> drivers/cxl/cxl.h | 6 ++++
>> drivers/cxl/port.c | 78 +++++++++++++++++++++++++++++++++++++++++
>> 4 files changed, 86 insertions(+), 73 deletions(-)
>>
>> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
>> index b50551601c2e..317cd0a91ffe 100644
>> --- a/drivers/cxl/core/pci.c
>> +++ b/drivers/cxl/core/pci.c
>> @@ -748,79 +748,6 @@ static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds)
>>
>> #ifdef CONFIG_PCIEAER_CXL
>>
>> -static void cxl_dport_map_rch_aer(struct cxl_dport *dport)
>> -{
>> - resource_size_t aer_phys;
>> - struct device *host;
>> - u16 aer_cap;
>> -
>> - aer_cap = cxl_rcrb_to_aer(dport->dport_dev, dport->rcrb.base);
>> - if (aer_cap) {
>> - host = dport->reg_map.host;
>> - aer_phys = aer_cap + dport->rcrb.base;
>> - dport->regs.dport_aer = devm_cxl_iomap_block(host, aer_phys,
>> - sizeof(struct aer_capability_regs));
>> - }
>> -}
>> -
>> -static void cxl_dport_map_ras(struct cxl_dport *dport)
>> -{
>> - struct cxl_register_map *map = &dport->reg_map;
>> - struct device *dev = dport->dport_dev;
>> -
>> - if (!map->component_map.ras.valid)
>> - dev_dbg(dev, "RAS registers not found\n");
>> - else if (cxl_map_component_regs(map, &dport->regs.component,
>> - BIT(CXL_CM_CAP_CAP_ID_RAS)))
>> - dev_dbg(dev, "Failed to map RAS capability.\n");
>> -}
>> -
>> -static void cxl_disable_rch_root_ints(struct cxl_dport *dport)
>> -{
>> - void __iomem *aer_base = dport->regs.dport_aer;
>> - u32 aer_cmd_mask, aer_cmd;
>> -
>> - if (!aer_base)
>> - return;
>> -
>> - /*
>> - * Disable RCH root port command interrupts.
>> - * CXL 3.0 12.2.1.1 - RCH Downstream Port-detected Errors
>> - *
>> - * This sequence may not be necessary. CXL spec states disabling
>> - * the root cmd register's interrupts is required. But, PCI spec
>> - * shows these are disabled by default on reset.
>> - */
>> - aer_cmd_mask = (PCI_ERR_ROOT_CMD_COR_EN |
>> - PCI_ERR_ROOT_CMD_NONFATAL_EN |
>> - PCI_ERR_ROOT_CMD_FATAL_EN);
>> - aer_cmd = readl(aer_base + PCI_ERR_ROOT_COMMAND);
>> - aer_cmd &= ~aer_cmd_mask;
>> - writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND);
>> -}
>> -
>> -/**
>> - * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport
>> - * @dport: the cxl_dport that needs to be initialized
>> - * @host: host device for devm operations
>> - */
>> -void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host)
>> -{
>> - dport->reg_map.host = host;
>> - cxl_dport_map_ras(dport);
>> -
>> - if (dport->rch) {
>> - struct pci_host_bridge *host_bridge = to_pci_host_bridge(dport->dport_dev);
>> -
>> - if (!host_bridge->native_aer)
>> - return;
>> -
>> - cxl_dport_map_rch_aer(dport);
>> - cxl_disable_rch_root_ints(dport);
>> - }
>> -}
>> -EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL");
>> -
>> static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds,
>> struct cxl_dport *dport)
>> {
>> diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
>> index 5ca7b0eed568..b8e767a9571c 100644
>> --- a/drivers/cxl/core/regs.c
>> +++ b/drivers/cxl/core/regs.c
>> @@ -199,6 +199,7 @@ void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
>>
>> return ret_val;
>> }
>> +EXPORT_SYMBOL_NS_GPL(devm_cxl_iomap_block, "CXL");
>>
>> int cxl_map_component_regs(const struct cxl_register_map *map,
>> struct cxl_component_regs *regs,
>> @@ -517,6 +518,7 @@ u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb)
>>
>> return offset;
>> }
>> +EXPORT_SYMBOL_NS_GPL(cxl_rcrb_to_aer, "CXL");
>>
>> static resource_size_t cxl_rcrb_to_linkcap(struct device *dev, struct cxl_dport *dport)
>> {
>> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
>> index ba08b77b65da..0dc43bfba76a 100644
>> --- a/drivers/cxl/cxl.h
>> +++ b/drivers/cxl/cxl.h
>> @@ -313,6 +313,12 @@ int cxl_setup_regs(struct cxl_register_map *map);
>> struct cxl_dport;
>> resource_size_t cxl_rcd_component_reg_phys(struct device *dev,
>> struct cxl_dport *dport);
>> +
>> +u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb);
>> +
>> +void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
>> + resource_size_t length);
>> +
>> int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport *dport);
>>
>> #define CXL_RESOURCE_NONE ((resource_size_t) -1)
>> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
>> index fe4b593331da..7b61f09347a5 100644
>> --- a/drivers/cxl/port.c
>> +++ b/drivers/cxl/port.c
>> @@ -6,6 +6,7 @@
>>
>> #include "cxlmem.h"
>> #include "cxlpci.h"
>> +#include "cxl.h"
>>
>> /**
>> * DOC: cxl port
>> @@ -57,6 +58,83 @@ static int discover_region(struct device *dev, void *unused)
>> return 0;
>> }
>>
>> +#ifdef CONFIG_PCIEAER_CXL
>> +
>> +static void cxl_dport_map_rch_aer(struct cxl_dport *dport)
>> +{
>> + resource_size_t aer_phys;
>> + struct device *host;
>> + u16 aer_cap;
>> +
>> + aer_cap = cxl_rcrb_to_aer(dport->dport_dev, dport->rcrb.base);
>> + if (aer_cap) {
>> + host = dport->reg_map.host;
>> + aer_phys = aer_cap + dport->rcrb.base;
>> + dport->regs.dport_aer = devm_cxl_iomap_block(host, aer_phys,
>> + sizeof(struct aer_capability_regs));
>> + }
>> +}
>> +
>> +static void cxl_dport_map_ras(struct cxl_dport *dport)
>> +{
>> + struct cxl_register_map *map = &dport->reg_map;
>> + struct device *dev = dport->dport_dev;
>> +
>> + if (!map->component_map.ras.valid)
>> + dev_dbg(dev, "RAS registers not found\n");
>> + else if (cxl_map_component_regs(map, &dport->regs.component,
>> + BIT(CXL_CM_CAP_CAP_ID_RAS)))
>> + dev_dbg(dev, "Failed to map RAS capability.\n");
>> +}
>> +
>> +static void cxl_disable_rch_root_ints(struct cxl_dport *dport)
>> +{
>> + void __iomem *aer_base = dport->regs.dport_aer;
>> + u32 aer_cmd_mask, aer_cmd;
>> +
>> + if (!aer_base)
>> + return;
>> +
>> + /*
>> + * Disable RCH root port command interrupts.
>> + * CXL 3.0 12.2.1.1 - RCH Downstream Port-detected Errors
>> + *
>> + * This sequence may not be necessary. CXL spec states disabling
>> + * the root cmd register's interrupts is required. But, PCI spec
>> + * shows these are disabled by default on reset.
>> + */
>> + aer_cmd_mask = (PCI_ERR_ROOT_CMD_COR_EN |
>> + PCI_ERR_ROOT_CMD_NONFATAL_EN |
>> + PCI_ERR_ROOT_CMD_FATAL_EN);
>> + aer_cmd = readl(aer_base + PCI_ERR_ROOT_COMMAND);
>> + aer_cmd &= ~aer_cmd_mask;
>> + writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND);
>> +}
>> +
>> +/**
>> + * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport
>> + * @dport: the cxl_dport that needs to be initialized
>> + * @host: host device for devm operations
>> + */
>> +void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host)
>> +{
>> + dport->reg_map.host = host;
>> + cxl_dport_map_ras(dport);
>> +
>> + if (dport->rch) {
>> + struct pci_host_bridge *host_bridge = to_pci_host_bridge(dport->dport_dev);
>> +
>> + if (!host_bridge->native_aer)
>> + return;
>> +
>> + cxl_dport_map_rch_aer(dport);
>> + cxl_disable_rch_root_ints(dport);
>> + }
>> +}
>> +EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL");
>> +
>> +#endif /* CONFIG_PCIEAER_CXL */
>> +
>> static int cxl_switch_port_probe(struct cxl_port *port)
>> {
>> struct cxl_hdm *cxlhdm;
