On 6/4/2025 2:06 PM, Sathyanarayanan Kuppuswamy wrote: > On 6/3/25 10:22 AM, Terry Bowman wrote: >> CXL and AER drivers need the ability to identify CXL devices. >> >> Add set_pcie_cxl() with logic checking for CXL Flexbus DVSEC presence. The >> CXL Flexbus DVSEC presence is used because it is required for all the CXL >> PCIe devices.[1] >> >> Add boolean 'struct pci_dev::is_cxl' with the purpose to cache the CXL >> Flexbus presence. >> >> Add function pcie_is_cxl() to return 'struct pci_dev::is_cxl'. >> >> [1] CXL 3.1 Spec, 8.1.1 PCIe Designated Vendor-Specific Extended >> Capability (DVSEC) ID Assignment, Table 8-2 >> >> Signed-off-by: Terry Bowman <terry.bowman@xxxxxxx> >> Reviewed-by: Ira Weiny <ira.weiny@xxxxxxxxx> >> --- > Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@xxxxxxxxxxxxxxx> > Thanks for reviewing Kuppuswamy. Terry
