> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@xxxxxxxxxx>
> Sent: 21 May 2025 15:18
> To: Shradha Todi <shradha.t@xxxxxxxxxxx>
> Cc: linux-pci@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linux-samsung-soc@xxxxxxxxxxxxxx;
> linux-kernel@xxxxxxxxxxxxxxx; linux-phy@xxxxxxxxxxxxxxxxxxx; manivannan.sadhasivam@xxxxxxxxxx; lpieralisi@xxxxxxxxxx;
> kw@xxxxxxxxx; robh@xxxxxxxxxx; bhelgaas@xxxxxxxxxx; jingoohan1@xxxxxxxxx; krzk+dt@xxxxxxxxxx; conor+dt@xxxxxxxxxx;
> alim.akhtar@xxxxxxxxxxx; vkoul@xxxxxxxxxx; kishon@xxxxxxxxxx; arnd@xxxxxxxx; m.szyprowski@xxxxxxxxxxx;
> jh80.chung@xxxxxxxxxxx
> Subject: Re: [PATCH 09/10] PCI: exynos: Add support for Tesla FSD SoC
>
> On Mon, May 19, 2025 at 01:01:51AM GMT, Shradha Todi wrote:
> > static int exynos_pcie_probe(struct platform_device *pdev) {
> > struct device *dev = &pdev->dev;
> > @@ -355,6 +578,26 @@ static int exynos_pcie_probe(struct platform_device *pdev)
> > if (IS_ERR(ep->phy))
> > return PTR_ERR(ep->phy);
> >
> > + if (ep->pdata->soc_variant == FSD) {
> > + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
> > + if (ret)
> > + return ret;
> > +
> > + ep->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
> > + "samsung,syscon-pcie");
> > + if (IS_ERR(ep->sysreg)) {
> > + dev_err(dev, "sysreg regmap lookup failed.\n");
> > + return PTR_ERR(ep->sysreg);
> > + }
> > +
> > + ret = of_property_read_u32_index(dev->of_node, "samsung,syscon-pcie", 1,
> > + &ep->sysreg_offset);
> > + if (ret) {
> > + dev_err(dev, "couldn't get the register offset for syscon!\n");
>
> So all MMIO will go via syscon? I am pretty close to NAKing all this, but let's be sure that I got it right - please post your complete DTS
> for upstream. That's a requirement from me for any samsung drivers - I don't want to support fake, broken downstream solutions
> (based on multiple past submissions).
>
By all MMIO do you mean DBI read/write? The FSD hardware architecture is such that the DBI/ATU/DMA address is at the same offset.
The syscon register holds the upper bits of the actual address differentiating between these 3 spaces. This kind of implementation was done
to reduce address space for PCI DWC controller. So yes, each DBI/ATU register read/write will have syscon write before it to switch address space.
> Best regards,
> Krzysztof
