On Tue, 20 May 2025 00:04:47 +0800, Hans Zhang wrote: > Update the PCI Endpoint (EP) device tree binding documentation to > include PCIe Gen5 and Gen6 support for the `max-link-speed` property. > Similar to the Host Controller binding, the original EP binding > limited this value to 1~4 (Gen1~Gen4). With current SOCs requiring > Gen5/Gen6 support (e.g., Synopsys/Cadence IP), this change aligns > the EP binding with the kernel's PCIe 6.0 capabilities. > > Signed-off-by: Hans Zhang <18255117159@xxxxxxx> > --- > Documentation/devicetree/bindings/pci/pci-ep.yaml | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Acked-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
