On 5/27/25 9:20 AM, Ziyue Zhang wrote: > From: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx> > > Add configurations in devicetree for PCIe0, including registers, clocks, > interrupts and phy setting sequence. > > Add PCIe lane equalization preset properties for 8 GT/s. > > Signed-off-by: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx> > Signed-off-by: Ziyue Zhang <quic_ziyuzhan@xxxxxxxxxxx> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx> Konrad
