On Thu, May 15, 2025 at 6:57 AM Manivannan Sadhasivam
<manivannan.sadhasivam@xxxxxxxxxx> wrote:
>
> On Mon, May 12, 2025 at 10:42:20PM +0200, Marek Vasut wrote:
> > On 5/9/25 9:37 PM, Manivannan Sadhasivam wrote:
> > > On Sun, Apr 06, 2025 at 04:45:21PM +0200, Marek Vasut wrote:
> > > > Document 'aux' clock which are used to supply the PCIe bus. This
> > > > is useful in case of a hardware setup, where the PCIe controller
> > > > input clock and the PCIe bus clock are supplied from the same
> > > > clock synthesiser, but from different differential clock outputs:
> > >
> > > How different is this clock from the 'reference clock'? I'm not sure what you
> > > mean by 'PCIe bus clock' here. AFAIK, endpoint only takes the reference clock
> > > and the binding already has 'ref' clock for that purpose. So I don't understand
> > > how this new clock is connected to the endpoint device.
> >
> > See the ASCII art below , CLK_DIF0 is 'ref' clock that feeds the controller
> > side, CLK_DIF1 is the bus (or 'aux') clock which feeds the bus (or endpoint)
> > side. Both clock come from the same clock synthesizer, but from two separate
> > clock outputs of the synthesizer.
> >
>
> Okay. So separate refclks are suppplied to the host and endpoint here and no,
> you should not call the other one as 'aux' clock, it is still the refclk. In
> this case, you should describe the endpoint refclk in the PCIe bridge node:
>
> pcie@... {
> clock = <refclk_host>;
> ...
>
> pcie@0 {
> device_type = "pci";
> reg = <0x0 0x0 0x0 0x0 0x0>;
> bus-range = <0x01 0xff>;
> clock = <refclk_ep>;
> ...
> };
> };
>
>
> and use the pwrctrl driver PCI_PWRCTRL_SLOT to enable it. Right now, the slot
> pwrctrl driver is not handling the refclk, but I can submit a patch for that.
There's another discussion about PCIe clocks here[1]. Seems there's a
variety of options here with spread-spectrum layered on top.
Rob
[1] https://lore.kernel.org/all/20250425092012.95418-2-cassel@xxxxxxxxxx
