On 5/7/25 5:15 AM, Ziyue Zhang wrote: > From: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx> > > Add configurations in devicetree for PCIe0, including registers, clocks, > interrupts and phy setting sequence. > > Add PCIe lane equalization preset properties for 8 GT/s. > > Signed-off-by: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx> > Signed-off-by: Ziyue Zhang <quic_ziyuzhan@xxxxxxxxxxx> > --- [...] > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0x7>; > + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; You added too many zeroes after &intc, this could not have worked [...] > + > + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555 > + 0x5555 0x5555 0x5555 0x5555>; very odd indentation, please put the 0x's under each other Konrad
