On Wed, Apr 23 2025 at 10:23, Lukas Wunner wrote:
> On Tue, Apr 22, 2025 at 04:07:05PM -0500, Bjorn Helgaas wrote:
>> This from an arm64 system is even more obscure to me:
>>
>> NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
>> GICv3: 256 SPIs implemented
>> Root IRQ handler: gic_handle_irq
>> GICv3: GICv3 features: 16 PPIs
>> kvm [1]: vgic interrupt IRQ18
>> xhci-hcd xhci-hcd.0.auto: irq 67, io mem 0xfe800000
>>
>> I have no clue where irq 67 goes.
>
> There's quite a bit of information available in /proc/interrupts,
> /proc/irq/ and /sys/kernel/irq/, I guess that's what most people use.
/sys/kernel/debug/irq/....
Gives the most comprehensive insight into the domain hierarchy.
# cat /sys/kernel/debug/irq/irqs/204
handler: handle_edge_irq
device: 0000:01:00.0
status: 0x00000000
istate: 0x00004000
ddepth: 0
wdepth: 0
dstate: 0x1d401200
IRQD_ACTIVATED
IRQD_IRQ_STARTED
IRQD_SINGLE_TARGET
IRQD_AFFINITY_SET
IRQD_AFFINITY_ON_ACTIVATE
IRQD_CAN_RESERVE
IRQD_HANDLE_ENFORCE_IRQCTX
node: 0
affinity: 50
effectiv: 50
pending:
domain: PCI-MSIX-0000:01:00.0-12
hwirq: 0x65
chip: PCI-MSIX-0000:01:00.0
flags: 0x1430
IRQCHIP_SKIP_SET_WAKE
IRQCHIP_ONESHOT_SAFE
IRQCHIP_MOVE_DEFERRED
address_hi: 0x00000000
address_lo: 0xfee32000
msg_data: 0x00000023
parent:
domain: VECTOR
hwirq: 0xcc
chip: APIC
flags: 0x0
Vector: 35
Target: 50
move_in_progress: 0
is_managed: 0
can_reserve: 1
has_reserved: 0
cleanup_pending: 0
It shows the complete domain hierarchy for each interrupt an
irq/domains/.... gives extra information about the domains.
You need to enable GENERIC_IRQ_DEBUGFS.
Exposing this in dmesg in a comprehensible and condensed form might be
possible, but needs some thought.
So far I survived pretty good with the debugfs data.
Thanks,
tglx
