On Wed, 16 Apr 2025 16:13:07 +0800, Richard Zhu wrote: > Add some enhancements for i.MX95 PCIe. > - Refine the link procedure to speed up link training. > - Add two ERRATA SW workarounds. > - To align PHY's power on sequency, add COLD reset. > - Add PLL clock lock check. > - Save/retore the LUT table in supend/resume callbacks. > - 3/7 relies on "arm64: dts: imx95: Correct the range of PCIe app-reg region" > https://lore.kernel.org/imx/20250314060104.390065-1-hongxing.zhu@xxxxxxx/ > > [...] Applied, thanks! [1/7] PCI: imx6: Start link directly when workaround is not required commit: 9c03e30e3ade32136fed5a4ab7872dcb205687d3 [2/7] PCI: imx6: Skip one dw_pcie_wait_for_link() in workaround link training commit: 4a4be0c088e3029a482ef8ac98bb2acb94af960e [3/7] PCI: imx6: Toggle the cold reset for i.MX95 PCIe commit: 47f54a902dcd3b756e8e761f2c4c742af57dfff0 [4/7] PCI: imx6: Workaround i.MX95 PCIe may not exit L23 ready commit: ce0c43e855c7f652b6351110aaaabf9b521debd7 [5/7] PCI: imx6: Let i.MX95 PCIe compliance with 8GT/s Receiver Impedance ECN commit: 744a1c20ce933dcaca0f161fe7da115902a2f343 [6/7] PCI: imx6: Add PLL clock lock check for i.MX95 PCIe commit: 047e8b6b3bc3e6b25bfa12896a39d9fb82b591be [7/7] PCI: imx6: Save and restore the LUT setting for i.MX95 PCIe commit: e4d66131caaf18d7c3c69914513f4be0519ddaaf Best regards, -- Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
