On 4/25/25 2:00 PM, George Moussalem via B4 Relay wrote:
> From: Nitheesh Sekar <quic_nsekar@xxxxxxxxxxx>
>
> Add phy and controller nodes for a 2-lane Gen2 and
> a 1-lane Gen2 PCIe bus. IPQ5018 has 8 MSI SPI interrupts and
> one global interrupt.
>
> NOTE: the PCIe controller supports gen3, yet the phy is limited to gen2.
>
> Signed-off-by: Nitheesh Sekar <quic_nsekar@xxxxxxxxxxx>
> Signed-off-by: Sricharan R <quic_srichara@xxxxxxxxxxx>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>
> Signed-off-by: George Moussalem <george.moussalem@xxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 246 +++++++++++++++++++++++++++++++++-
> 1 file changed, 244 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> index 8914f2ef0bc47fda243b19174f77ce73fc10757d..917c6eb7c227e405e9216125cff15551f57839a5 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> @@ -147,6 +147,40 @@ usbphy0: phy@5b000 {
> status = "disabled";
> };
>
> + pcie1_phy: phy@7e000{
"@7e000 {"
[...]
> + pcie0_phy: phy@86000{
ditto
[...]
> +
> + /*
> + * While the PCIe controller supports gen3,
> + * the phy is limited to gen2. Hence, limit
> + * the link speed to gen2.
> + */
/* The controller supports Gen3, but the connected PHY is only Gen2-capable */
and it nicely fits into 1 line!
With that:
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
Konrad
