On Thu, Mar 13, 2025 at 05:10:12PM +0530, Krishna Chaitanya Chundru wrote:
> QCOM PCIe controllers need to disable ASPM before initiating link
> re-train. So as part of pre_bw_scale() disable ASPM and as part of
> post_scale_bus_bw() enable ASPM back.
>
> Update ICC & OPP votes based on the requested speed so that RPMh votes
> get updated based on the speed.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 49 ++++++++++++++++++++++++++++++++++
> 1 file changed, 49 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index b66c413f1e2b..a68e62422ff7 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1328,10 +1328,59 @@ static int qcom_pcie_set_icc_opp(struct qcom_pcie *pcie, int speed, int width)
> return ret;
> }
>
> +static int qcom_pcie_scale_bw(struct dw_pcie_rp *pp, int speed)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct qcom_pcie *pcie = to_qcom_pcie(pci);
> + u32 offset, status, width;
> +
> + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> + status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
> +
> + width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status);
> +
> + return qcom_pcie_set_icc_opp(pcie, speed, width);
> +}
> +
> +static int qcom_pcie_enable_disable_aspm(struct pci_dev *pdev, void *userdata)
qcom_pcie_enable_aspm() since the opaque argument is serving as a boolean.
> +{
> + bool *enable = userdata;
> +
> + /*
> + * QCOM controllers doesn't support link re-train with ASPM enabled.
> + * Disable ASPM as part of pre_bus_bw() and enable them back as
> + * part of post_bus_bw().
> + */
> + if (*enable)
> + pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL);
> + else
> + pci_disable_link_state_locked(pdev, PCIE_LINK_STATE_ALL);
> +
> + return 0;
> +}
> +
> +static void qcom_pcie_host_post_scale_bus_bw(struct dw_pcie_rp *pp, int current_speed)
> +{
> + bool enable = true;
> +
> + pci_walk_bus(pp->bridge->bus, qcom_pcie_enable_disable_aspm, &enable);
We do not enable ASPM on all platforms. So this is going to affect all platforms
whose client drivers initiate link retrain.
- Mani
--
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