On Thu, Apr 17, 2025 at 03:18:26PM +0200, Christian Bruel wrote:
> Add driver for the STM32MP25 SoC PCIe Gen1 2.5 GT/s and Gen2 5GT/s
> controller based on the DesignWare PCIe core.
> +static void stm32_pcie_deassert_perst(struct stm32_pcie *stm32_pcie)
> +{
> + /* Delay PERST# de-assertion t least 100ms he power to become stable */
s/ t / at /
s/ he / for / ?
Could also remove "100ms".
> + msleep(PCIE_T_PVPERL_MS);
> +
> + gpiod_set_value(stm32_pcie->perst_gpio, 0);
> +
> + /* Wait 100ms for the REFCLK to becode stable */
s/becode/become/
Could drop "100ms" here, too.
> + if (stm32_pcie->perst_gpio)
> + msleep(PCIE_T_RRS_READY_MS);
> +}
> + if (stm32_pcie->wake_gpio) {
> + wake_irq = gpiod_to_irq(stm32_pcie->wake_gpio);
> + ret = dev_pm_set_dedicated_wake_irq(dev, wake_irq);
> + if (ret) {
> + dev_info(dev, "Failed to enable wake# %d\n", ret);
I guess this refers to the "WAKE#" signal in the spec? Could
capitalize to remove the question.
