On Fri, Apr 11, 2025 at 01:22:39PM +0200, Konrad Dybcio wrote: > On 3/17/25 11:00 AM, Varadarajan Narayanan wrote: > > From: Praveenkumar I <quic_ipkumar@xxxxxxxxxxx> > > > > Add phy and controller nodes for pcie0_x1 and pcie1_x2. > > > > Signed-off-by: Praveenkumar I <quic_ipkumar@xxxxxxxxxxx> > > Signed-off-by: Varadarajan Narayanan <quic_varada@xxxxxxxxxxx> > > --- > > [...] > > I think you're reaching out of the BAR register space by an order of magnitude, > on both hosts > > IIUC it's only 32 MiB for both Checked with h/w person and he confirmed that the BAR register space is correct. It is 256MB for one and 128MB for the other controller. > the register addresses/sizes look good Ok. Thanks Varada > I'm not super glad that we decided to move forward with not putting PARF first, > as the other registers are in the BAR region, but bindings are bindings and > bindings are ABI.. > > Konrad
