Hi, On 22:52 Wed 19 Mar , Andrea della Porta wrote: > RP1 is an MFD chipset that acts as a south-bridge PCIe endpoint sporting > a pletora of subdevices (i.e. Ethernet, USB host controller, I2C, PWM, > etc.) whose registers are all reachable starting from an offset from the > BAR address. The main point here is that while the RP1 as an endpoint > itself is discoverable via usual PCI enumeraiton, the devices it contains > are not discoverable and must be declared e.g. via the devicetree. > ... since there has been no feedback for a while, a gentle reminder about this patchset. Several patches have at least one Reviewed-by tag, with the exception of: - PATCH 5, 8: those are, respectively, the driver for RP1 clock and misc core which have no major rework since the inception. - PATCH 9, 10: those are new patches, where the most relevant change is a rearrangement of the dts include hierarchy to be flexible enough to support both the dtb overlay approach and the monolithic dtb. - PATCH 13: just enables OF_OVERLAY config option. Some metric data have been added to help evaluating the impact. Many thanks, Andrea
