On Tue, Apr 01, 2025 at 10:17:10AM +0100, Marc Zyngier wrote: > From: Hector Martin <marcan@xxxxxxxxx> > > This is checking a core refclk in per-port setup which doesn't make a > lot of sense, and the bootloader needs to have gone through this anyway. > > It doesn't work on T602x, so just drop it across the board. > > Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx> > Acked-by: Alyssa Rosenzweig <alyssa@xxxxxxxxxxxxx> > Tested-by: Janne Grunau <j@xxxxxxxxxx> > Signed-off-by: Hector Martin <marcan@xxxxxxxxx> > Signed-off-by: Alyssa Rosenzweig <alyssa@xxxxxxxxxxxxx> > Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> - Mani > --- > drivers/pci/controller/pcie-apple.c | 6 ------ > 1 file changed, 6 deletions(-) > > diff --git a/drivers/pci/controller/pcie-apple.c b/drivers/pci/controller/pcie-apple.c > index 94c49611b74df..c00ec0781fabc 100644 > --- a/drivers/pci/controller/pcie-apple.c > +++ b/drivers/pci/controller/pcie-apple.c > @@ -475,12 +475,6 @@ static int apple_pcie_setup_refclk(struct apple_pcie *pcie, > u32 stat; > int res; > > - res = readl_relaxed_poll_timeout(pcie->base + CORE_RC_PHYIF_STAT, stat, > - stat & CORE_RC_PHYIF_STAT_REFCLK, > - 100, 50000); > - if (res < 0) > - return res; > - > rmw_set(PHY_LANE_CTL_CFGACC, port->phy + PHY_LANE_CTL); > rmw_set(PHY_LANE_CFG_REFCLK0REQ, port->phy + PHY_LANE_CFG); > > -- > 2.39.2 > -- மணிவண்ணன் சதாசிவம்
