On Thu, Mar 27, 2025 at 10:59:08AM +0000, Manikandan Karunakaran Pillai wrote: > Enhances the exiting Cadence PCIe controller drivers to support second > generation PCIe controller also referred as HPA(High Performance > Architecture) controllers. > > The patch set enhances the Cadence PCIe driver for the new high > performance architecture changes. The "compatible" property in DTS > is added with more strings to support the new platform architecture > and the register maps that change with it. The driver read register > and write register functions take the updated offset stored from the > platform driver to access the registers. The driver now supports > the legacy and HPA architecture, with the legacy code being changed > minimal. The TI SoC continues to be supported with the changes > incorporated. The changes are also in tune with how multiple platforms > are supported in related drivers. > > Patch 1/7 - DTS related changes for property "compatible" > Patch 2/7 - Updates the header file with relevant register offsets and > bit definitions > Patch 3/7 - Platform related code changes > Patch 4/7 - PCIe EP related code changes > Patch 5/7 - Header file is updated with register offsets and updated > read and write register functions > Patch 6/7 - Support for multiple arch by using registered callbacks > Patch 7/7 - TIJ72X board is updated to use the new approach This one line patch summary is not useful. We can look into individual patches. > This series is v2. Please use version in the subject prefix and also include the changelog section. > Comments from the earlier patch submission on the same enhancements are > taken into consideration. The previous submitted patch links is > https://lore.kernel.org/lkml/CH2PPF4D26F8E1C205166209F012D4F3A81A2A42@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx/ > This is not how you would add changelog in cover letter. Please read: Documentation/process/submitting-patches.rst - Mani -- மணிவண்ணன் சதாசிவம்
