On Fri, Mar 28, 2025 at 03:58:32PM +0530, Krishna Chaitanya Chundru wrote: > As per PCIe spec 6.0.1, add PCIe lane equalization register offset for > data rates 8.0 GT/s, 32.0 GT/s and 64.0 GT/s. > > Add macro for defining data rate 64.0 GT/s physical layer capability ID. > > Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> - Mani > --- > include/uapi/linux/pci_regs.h | 12 +++++++++++- > 1 file changed, 11 insertions(+), 1 deletion(-) > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index 3445c4970e4d..0dcd9aba584d 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -749,7 +749,8 @@ > #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */ > #define PCI_EXT_CAP_ID_PL_32GT 0x2A /* Physical Layer 32.0 GT/s */ > #define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */ > -#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_DOE > +#define PCI_EXT_CAP_ID_PL_64GT 0x31 /* Physical Layer 64.0 GT/s */ > +#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_64GT > > #define PCI_EXT_CAP_DSN_SIZEOF 12 > #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 > @@ -1140,12 +1141,21 @@ > #define PCI_DLF_CAP 0x04 /* Capabilities Register */ > #define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */ > > +/* Secondary PCIe Capability 8.0 GT/s */ > +#define PCI_SECPCI_LE_CTRL 0x0c /* Lane Equalization Control Register */ > + > /* Physical Layer 16.0 GT/s */ > #define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ > #define PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK 0x0000000F > #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0 > #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4 > > +/* Physical Layer 32.0 GT/s */ > +#define PCI_PL_32GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ > + > +/* Physical Layer 64.0 GT/s */ > +#define PCI_PL_64GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ > + > /* Native PCIe Enclosure Management */ > #define PCI_NPEM_CAP 0x04 /* NPEM capability register */ > #define PCI_NPEM_CAP_CAPABLE 0x00000001 /* NPEM Capable */ > > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்
