> -----Original Message-----
> From: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> Sent: 2025年4月2日 14:36
> To: Hongxing Zhu <hongxing.zhu@xxxxxxx>
> Cc: Frank Li <frank.li@xxxxxxx>; l.stach@xxxxxxxxxxxxxx; lpieralisi@xxxxxxxxxx;
> kw@xxxxxxxxx; robh@xxxxxxxxxx; bhelgaas@xxxxxxxxxx;
> shawnguo@xxxxxxxxxx; s.hauer@xxxxxxxxxxxxxx; kernel@xxxxxxxxxxxxxx;
> festevam@xxxxxxxxx; linux-pci@xxxxxxxxxxxxxxx;
> linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; imx@xxxxxxxxxxxxxxx;
> linux-kernel@xxxxxxxxxxxxxxx
> Subject: Re: [PATCH v3 2/6] PCI: imx6: Toggle the cold reset for i.MX95 PCIe
>
> On Fri, Mar 28, 2025 at 11:02:09AM +0800, Richard Zhu wrote:
> > Add the cold reset toggle for i.MX95 PCIe to align PHY's power up sequency.
>
> What do you mean by 'cold' reset? Is it 'core' reset? I see both terminologies
> used in the code.
>
Regarding my understands, the cold reset is one reset category of the core reset.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
> > ---
> > drivers/pci/controller/dwc/pci-imx6.c | 42
> > +++++++++++++++++++++++++++
> > 1 file changed, 42 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> > b/drivers/pci/controller/dwc/pci-imx6.c
> > index 57aa777231ae..6051b3b5928f 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -71,6 +71,9 @@
> > #define IMX95_SID_MASK GENMASK(5, 0)
> > #define IMX95_MAX_LUT 32
> >
> > +#define IMX95_PCIE_RST_CTRL 0x3010
> > +#define IMX95_PCIE_COLD_RST BIT(0)
> > +
> > #define to_imx_pcie(x) dev_get_drvdata((x)->dev)
> >
> > enum imx_pcie_variants {
> > @@ -773,6 +776,43 @@ static int imx7d_pcie_core_reset(struct imx_pcie
> *imx_pcie, bool assert)
> > return 0;
> > }
> >
> > +static int imx95_pcie_core_reset(struct imx_pcie *imx_pcie, bool
> > +assert) {
> > + u32 val;
> > +
> > + if (assert) {
> > + /*
> > + * From i.MX95 PCIe PHY perspective, the COLD reset toggle
> > + * should be complete after power-up by the following sequence.
> > + * > 10us(at power-up)
> > + * > 10ns(warm reset)
> > + * |<------------>|
> > + * ______________
> > + * phy_reset ____/ \________________
> > + * ____________
> > + * ref_clk_en_______________________/
> > + * Toggle COLD reset aligned with this sequence for i.MX95 PCIe.
> > + */
> > + regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
> > + IMX95_PCIE_COLD_RST);
>
> Is this really COLD reset? Or CORE reset?
Cold reset is one reset type of core reset refer to my understand.
>
> > + /*
> > + * To make sure delay enough time, do regmap_read_bypassed
> > + * before udelay(). Since udelay() might not use MMIO, and cause
> > + * delay time less than setting value.
> > + */
>
> This comment could be rephrased:
>
> /*
> * Make sure the write to IMX95_PCIE_RST_CTRL is flushed to the
> * hardware by doing a read. Otherwise, there is no guarantee
> * that the write has reached the hardware before udelay().
> */
>
Okay
Best Regards
Richard Zhu
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்
