On Fri, Mar 28, 2025 at 11:02:12AM +0800, Richard Zhu wrote:
> Add PLL clock lock check for i.MX95 PCIe.
>
What are the implications of not waiting for PLL lock? I guess clock
instability.
> Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
> Reviewed-by: Frank Li <Frank.Li@xxxxxxx>
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 28 +++++++++++++++++++++++++--
> 1 file changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 35194b543551..40eeb02ffb5d 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -45,6 +45,9 @@
> #define IMX95_PCIE_PHY_GEN_CTRL 0x0
> #define IMX95_PCIE_REF_USE_PAD BIT(17)
>
> +#define IMX95_PCIE_PHY_MPLLA_CTRL 0x10
> +#define IMX95_PCIE_PHY_MPLL_STATE BIT(30)
> +
> #define IMX95_PCIE_SS_RW_REG_0 0xf0
> #define IMX95_PCIE_REF_CLKEN BIT(23)
> #define IMX95_PCIE_PHY_CR_PARA_SEL BIT(9)
> @@ -479,6 +482,23 @@ static void imx7d_pcie_wait_for_phy_pll_lock(struct imx_pcie *imx_pcie)
> dev_err(dev, "PCIe PLL lock timeout\n");
> }
>
> +static int imx95_pcie_wait_for_phy_pll_lock(struct imx_pcie *imx_pcie)
> +{
> + u32 val;
> + struct device *dev = imx_pcie->pci->dev;
> +
> + if (regmap_read_poll_timeout(imx_pcie->iomuxc_gpr,
> + IMX95_PCIE_PHY_MPLLA_CTRL, val,
> + val & IMX95_PCIE_PHY_MPLL_STATE,
> + PHY_PLL_LOCK_WAIT_USLEEP_MAX,
> + PHY_PLL_LOCK_WAIT_TIMEOUT)) {
> + dev_err(dev, "PCIe PLL lock timeout\n");
> + return -ENODEV;
-ETIMEDOUT
- Mani
--
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