On 27/03/2025 18:25, Manivannan Sadhasivam wrote:
>> /**
>> @@ -551,6 +600,27 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port,
>> port->reg_base = port->cfg->win;
>> }
>>
>> + port->crx_base = devm_platform_ioremap_resource_byname(pdev,
>> + "cpm_crx");
>> + if (IS_ERR(port->crx_base)) {
>> + if (PTR_ERR(port->crx_base) == -EINVAL)
>> + port->crx_base = NULL;
>> + else
>> + return PTR_ERR(port->crx_base);
>> + }
>> +
>> + if (port->variant->version == CPM5NC_HOST) {
>> + port->cpm5nc_attr_base =
>> + devm_platform_ioremap_resource_byname(pdev,
>> + "cpm5nc_attr");
>
> Where is this resource defined in the binding?
>
So this is v6 and still not tested.
Where is the DTS using this binding and driver, so we can verify that
AMD is not sending us such totally bogus, downstream code?
Best regards,
Krzysztof
